JPS6320075B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for interframe encoding television signals.

In the digital transmission of television signals, the number of transmission bits is significantly reduced compared to when using normal PCM by using interframe coding, which encodes and transmits the differential signal of adjacent frames (bandwidth compression and This allows for a large compression ratio (ratio in which the number of transmitted bits is reduced compared to PCM), especially for pictures with small movements.
can be obtained. However, for pictures with large movements, there is a drawback that the compression ratio described above decreases because the difference signal between adjacent frames becomes large.

As a countermeasure to this problem, a technique called ``interframe coding that follows motion'' is being considered. As shown in Figure 1, this method detects the motion vector of an image, shifts the previous frame signal by the motion vector, takes the difference from the current frame signal, encodes the difference signal and motion vector, and transmits it. be. In this method, image motion detection is performed as follows. That is, the TV screen is divided into small blocks, each block is shifted with respect to the same position in the previous frame as a reference (this amount of shift is called a shift vector), the difference is calculated, and the evaluation function ( Various evaluation functions have been considered, such as the sum of the squares of the difference signals, the sum of the absolute values of the difference signals, or the number of cases where the absolute value of the difference signals exceeds a certain threshold value), and calculate the value of the evaluation function. Let the shift vector with the minimum value be the motion vector in that block. However, since quite large movements can occur in television signals, it is necessary to calculate the above-mentioned evaluation function for quite a large number of shift vectors, which requires a huge amount of calculation and requires a large-scale device. . For example, if we detect movement in the range of 8 samples left and right and 8 lines above and below (2×8+
The aforementioned evaluation function values are determined for 1)×(2×8+1)=289 shift vectors.

SUMMARY OF THE INVENTION In order to solve the above problems, it is an object of the present invention to provide an interframe coding apparatus using a motion detection technique that does not require a large increase in the scale of the apparatus even for a fairly wide range of motion.

Next, the present invention will be explained in detail with reference to the drawings.

A feature of the present invention is that the amount of required calculations is reduced by performing motion vector detection in multiple stages. Referring to FIG. 2 1, 2 and 3,
It shows how motion vectors are detected in three stages. In FIG. 2, a shift vector (x _N , y _N ) indicates that the previous frame signal is shifted to the right by x _N samples and upward by y _N lines.

First, in the first stage (Fig. 2 1), A,
The above-mentioned evaluation function values are determined for the first shift vector group indicated by B, C, D, and E, and among them, the shift vector with the minimum evaluation function value is determined. For example, if D is the shift vector that minimizes the evaluation function value among A to E, then in the second stage (Figure 2 2) the second shift vector placed near D
Evaluation function values are similarly determined for the shift vector group D ₁ to _{D 9} , and a shift vector with the minimum evaluation function value among D ₁ to _{D 9} is determined. If D ₉ has the minimum evaluation function, in the third stage (Fig. 3), the evaluation function is calculated for the third shift vector group D _9,1 to D _9,9 placed near D ₉ . Find the value that minimizes the evaluation function value, for example, D _9,5
Let D _9,5 be the motion vector for that block, no matter what is the minimum. At this time, the signal of the previous frame shifted by the shift vector D _9,5 is used as a predicted signal, and the difference signal between this predicted signal and the current frame signal and the shift vector D _9,5 are encoded and transmitted as a motion vector. . The above is a description of the encoding when D becomes the minimum evaluation function in the first stage, but motion estimation is performed in exactly the same way when other shift vectors become the minimum evaluation function. Furthermore, although the case of three-stage detection has been described here, the same applies even if there are more stages. As shown in FIG. 1, even if it is necessary to obtain evaluation functions for 200 or more shift vectors in the conventionally known method, according to the present invention, if the evaluation function is performed as shown in FIG. 5
It is only necessary to obtain evaluation functions for a total of 23 shift vectors, 9 in the second stage and 9 in the third stage, which can significantly reduce the amount of calculation required.

Next, examples of the present invention will be described. FIG. 3 is a block diagram showing the configuration of an interframe encoding device according to an embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of a decoding device.

In FIG. 3, if the output of the frame memory 14 is connected to the signal line 16 except for the predicted signal generator 11, the second encoder 18, and the multiplexer 20, the configuration becomes exactly the same as that of the conventional interframe encoding device. . Further, in FIG. 4, the demultiplexer 26, the second decoder 37 and the variable delay circuit 3
If the signal lines 25 and 27 and the signal lines 33 and 35 are the same signal line except for the signal line 4, the configuration will be exactly the same as the conventional interframe decoding device. Therefore,
In the following description, components specific to the present invention will be described in detail.

In FIG. 3, it is assumed that an A/D (analog-digital) converted television signal (hereinafter abbreviated as TV signal for simplicity) is input from terminal 1. A TV signal input from terminal 1 is given to delay circuit 3 and predictive signal generator 11 . The delay circuit 3 is used to synchronize the timing of the prediction signal output from the prediction signal generator 11 via the signal line 16 and the TV signal input from the terminal 1. The delayed TV signal output from the delay circuit 3 through the signal line 4 is subtracted by a subtracter 5 from the prediction signal output from the prediction signal generator 11 through the signal line 16, and this difference signal (prediction error signal ) is input to a quantizer 7 via a signal line 6, quantized, and input via a signal line 8 to a first encoder 9 and an adder 17.
Here, the first encoder 9 performs unequal length encoding on the quantized prediction error signal, similar to that used in a conventional interframe encoding device. The quantized prediction error signal inputted through the signal line 8 is encoded by the first encoder 9 and outputted to the signal line 10 . On the other hand, the quantized prediction error signal is given to the adder 17 via the signal line 8, added to the prediction signal output from the prediction signal generator 11 to the signal line 16, locally decoded, and sent via the signal line 13. The predicted signal generator 11 is used to generate a predicted signal in the next frame. The predicted signal generator 11 performs the above-mentioned multi-step detection of motion from the input television signal inputted via the signal line 2 and the signal of one frame before inputted via the signal line 15, and generates a predicted signal. is output to the signal line 16. Further, the predicted signal generating section 11 supplies a signal indicating a motion vector detected by multi-stage motion detection to the second encoder 18 via a signal line 19. second encoder 18
encodes the input signal, for example, encodes it into an unequal length encoder, and outputs the encoded signal to the signal line 12.

The encoded motion vector outputted to the signal line 12 is multiplexed with the encoded prediction error signal outputted to the signal line 10 in the multiplexer 20 and sent to the signal line 21. The multiplexed signal on the signal line 21 is written to a transmitting side buffer memory 22 for speed matching with the transmission speed of the transmission line, and the signal written to the transmitting side buffer memory 22 is read out at the transmission speed of the transmission line. Transmission line 2
Sent on 3rd.

Next, the decoding device will be explained with reference to FIG.

The signal output from the encoding device to the transmission path 23 is written to the receiving side buffer memory 24 at the transmission speed of the transmission path, is read out to the signal line 25 by the clock pulse of the decoding device, and is shown as a prediction error signal by the demultiplexer 26. The code and the code indicating the motion vector are separated and output to signal lines 27 and 28, respectively.

The code indicating the prediction error signal is decoded by the first decoder 36, and the prediction error signal is input to the adder 29 via the signal line 31. On the other hand, the shifted previous frame signal output from the variable delay circuit 34 is input to the adder 29 via the signal line 35.
As a result, the signals applied via the signal line 31 and the signal line 35 are added, and the TV signal is decoded and output to the signal line 30. Further, the signal on the signal line 30 is written into the frame memory 32 and used for decoding the TV signal of the next frame. Further, the signal read from the frame memory 32 is input to a variable delay circuit 34 (the configuration of which will be described later), and the shifted previous frame signal mentioned above is output.

On the other hand, the code indicating the motion vector outputted from the demultiplexer 26 to the signal line 28 is decoded by the second decoder 33, outputted to the signal line 39 as a shift control signal, and inputted to the variable delay circuit 34. . The variable delay circuit 34 shifts the signal applied via the signal line 33 in accordance with the shift control signal and outputs it to the adder 29 via the signal line. This decodes the TV signal.

Next, the predicted signal generating section 11 will be explained with reference to FIG. Note that an example in which a plurality of horizontal scanning lines of a TV signal are processed in parallel will be described below. The unit of this parallel processing matches the vertical size of the block (in this example, the block size is explained as 8 horizontal scanning lines x 16 pixels, so it is 8), but in particular, it is divided into scanning lines. Unless otherwise necessary for explanation, for example, a single thick line such as the signal line 45 in FIG. 5 will be used as a representative.

The input TV signal input from terminal 1 in FIG. is read out and output to the signal line 45.

A signal from one frame before is inputted from the frame memory 14 to the memory unit 41 via the signal line 15, and the control circuit 4
Shift control signals corresponding to the shift vector groups in each of the above-mentioned stages are inputted from 2 through signal lines 53 to 55. The memory unit 41 extracts the signal of the previous frame at a position shifted according to the shift control signal with reference to the position on the TV screen corresponding to the block of the current frame, and transfers the signal to the signal line 4.
6 to 48. That is, the previous frame signal shifted in response to the shift control signal on the signal line 53 is transferred to the signal line 46, and the previous frame signal shifted in response to the shift control signal on the signal line 54 is transferred to the signal line 47.
is output to. The same applies to the signal line 55 and the signal line 48.

The detector 43 uses the signal of the current frame sent via the signal line 45 and the signal group shifted by an amount corresponding to the shift vector at each stage of motion detection given via the signal lines 46 to 48.
At each stage, the aforementioned evaluation function value is transferred to the signal line 53.
55 to calculate the shift vector that minimizes the evaluation function value, and provides it to the control circuit 42 via the signal line 51 and the minimum value of the function value to the signal line 98.
The signal is applied to the control circuit 42 via the control circuit 42. However, signal line 5
If the control circuit 42 determines the shift vector of the next stage only by the shift control signal inputted through 1, it is not necessary to input the minimum value to the control circuit 42. An example of this case will be described below. The control circuit 42 sends a shift control signal indicating the next stage shift vector group belonging to the shift vector given via the signal line 51 to signal lines 53 to 5.
5 and supplies the memory address to the first memory 40 and memory section 41 via signal lines 50 and 49, respectively, to start the next stage of detection.

Further, at the time when the final stage of motion detection is completed, the control circuit 42 connects the signal line 5 from the detector 43 to the signal line 5.
The shift vector with the minimum evaluation function value given through 1 is directly transferred to signal lines 19 and 5.
It also supplies the address to the memory unit 41 via the signal line 49, outputs a signal obtained by shifting the signal of the previous frame according to the motion vector to the signal line 57, and supplies the address to the third memory 44. input. Also,
The control circuit 42 supplies the address to the third memory 44 via the signal line 52, and the prediction signal is written into the third memory 44. The prediction signal is read out from the third memory 44 and sent to the third memory 44 via the signal line 16.
It is applied to subtracter 5 and adder 17 in the figure. After the above operations are completed, the control circuit 42 outputs a shift control signal corresponding to the first stage shift vector to the signal lines 53 to 55, and also outputs a shift control signal corresponding to the first stage shift vector to the first memory 40 and the memory section 42 through the signal lines 49, The address of the next block is supplied via 50, and motion detection and prediction signal generation for the next block is performed.

Next, the operation of the memory section 41 will be explained with reference to FIG. The previous frame signal applied from the frame memory 14 in FIG. 3 via the signal line 15 is the second
, and is output to the signal line 64 every time an address signal and a read signal are input from the control circuit 42 via the signal line 49. Here, the number of signals output in parallel through the signal line 64 is based on the assumption that the vertical size of the block is 8 lines, and that motion detection is performed up to 8 lines above and below on the TV screen. Then it becomes 24.

The signal on the signal line 64 is transmitted to variable delay circuits 61 to 6.
given to 3. Here, the number of variable delay circuits matches the maximum number of shift vectors in each stage of motion detection if one stage of detection is performed in parallel in one operation (for example, In the example explained in Figure 2, the first stage has five pieces, the second stage
There are 9 stages and 9 third stages, so there are 9). It is also possible to perform the detection of one stage in multiple steps, but this case will be described later.

The variable delay circuits 61-63 extract the previous frame signals shifted according to the shift control signals inputted via the signal lines 53-55, respectively, from the signals inputted via the signal line 64, and output them to the signal lines 46-46, respectively. 48 to the detection circuit 43.

The variable delay circuits 61-63 will be explained with reference to FIG. However, variable delay circuits 61 to 63
Since the operations of both circuits are exactly the same, only the variable delay circuit 61 will be explained. In addition, in the above explanation, the signal line 64 is represented by one line in the drawings, but here, when data of 12 horizontal scanning lines is input to the variable delay circuit 61 in parallel (for example, A case where the vertical size is 4 horizontal scanning lines and motion detection is performed up to 4 horizontal scanning lines vertically will be described. Therefore, the signal line 64 is 64 ₁
〜64 Displayed separately as ₁₂ . In addition, in the above explanation, each of the signal lines 53 to 55 requires a number of lines corresponding to the number of bits necessary to express the maximum shift amount in each of the vertical and horizontal directions on the television screen. However, to simplify the explanation, I have used one line to represent it. Here, the line to which the horizontal shift control signal is sent is shown as 53 ₁ , and the line to which the vertical shift control signal is sent is shown as 53 ₂ .

In FIG. 7, it is assumed that signal lines 64 ₅ to 64 ₈ correspond to blocks of the current frame (i.e., when the vertical movement is 0, signal lines 64 5 to 64 8
The signal above ₅ to 64 ₈ is selected as the predicted signal).
Also, for convenience, it is defined that the smaller the subscript _N of 64N is, the higher it is on the TV screen.

When a control signal is sent to shift the signal line 53 ₂ up one line in the vertical direction and output it, the multiplexer 70 outputs the signal on the signal line 64 ₄ to the signal line 82 , and the multiplexer 71 outputs the signal on the signal line 64 4 .
_Similarly , the multiplexers 72 and 73 output the signals 64 6 and 64 7 to the signal lines 64 ₆ and 64 ₇ respectively.
The signals are output to signal lines 84 and 85. Similarly, when a vertical shift control signal with another value is input, the signal on the signal line at a position shifted by that value with respect to the signal lines 64 ₅ - 64 ₈ is transferred to the signal lines 82 - 8 .
5 is output.

The operation of the circuit composed of the multiplexers 70 to 73 explained above is basically based on POSITION
SCALER (e.g. 1976 by Signatex)
“SIGNETICS DATA” published in
MANUAL” page 267-page 270-8-BIT
POSITION SCALER N8243), so if the number of parallel output lines of memory B60 in FIG. 6 is small, the above-mentioned integrated circuit can also be used.

In Figure 7, reference numerals 86, 87, 88
Since the operations of the parts indicated by reference numeral 86 and 89 are exactly the same, the operation of the part indicated by reference numeral 86 will be explained.

The signal output to the signal line 82 is input to the shift register 47 with taps. Here, the number of taps of this shift register is determined by the maximum range of velocity detection in the lateral direction. For example, when detecting lateral movement up to 8 samples left and right, the number of taps is 17. The signals output from each tap of shift register 74 are applied in parallel to multiplexer 78. The multiplexer 78 outputs one of each input to the signal line 46 ₁ in response to the horizontal shift control signal input via the signal line 53 ₁ . In this way, it is possible to obtain the previous frame signal shifted in response to the shift control signals on the signal lines 53 ₁ and 53 ₂ with respect to the current frame signal block.

Here, the variable delay circuit 3 of the decoding device shown in FIG.
In addition to configuration 2, since the output of this variable delay circuit 32 is in units of one horizontal scanning line, this circuit 32 is similar to the variable delay circuit 3 on the transmitting side shown in FIG.
(In this case, the signal of the signal line corresponding to the position of the signal line _94-5 has a vertical movement of 0.
).

Next, the operation of the detector 43 will be explained with reference to FIG. As described in relation to the memory section 41, in the present invention, two configurations can be considered, depending on whether the detection of one stage is performed in one parallel operation or in several times. , First, we will discuss the case where one stage is detected by one parallel operation (in this case, register 102 and register 103 are unnecessary. Also, signal line 101 and signal line 98, signal line 51 and signal line are the same signal line).

The signals on the signal lines 46 to 48 are respectively sent to the calculation unit 9.
2 to 94 are input. On the other hand, calculation units 92 to 94
The signal of the block of the current frame is input to the signal line 45, and the above-mentioned evaluation function value is calculated. The calculation results are provided to the comparator 100 via signal lines 95 to 97, respectively. In addition, the comparison section 100
A shift control signal (corresponding to the shift amount of the shifted previous frame signal input via signal lines 46 to 48, respectively) is inputted to via signal lines 53 to 55, and the comparator 100 The evaluation function values input via signal lines 95 to 97 are compared, and a shift control signal corresponding to the one with the smallest evaluation function value is output to the signal line 51 (for example, the evaluation function values input via signal line 95 If the value is the minimum, the shift control signal on the signal line 53 is output to the signal line 51).

Next, a case will be described in which one stage of detection is divided into several times. However, since the operations of the calculation units 92 to 94 are exactly the same, a description thereof will be omitted. In this case, the minimum value of the evaluation function values input via the first signal lines 95 to 97 is the signal line 101.
is applied to register 102 via. Further, a shift control signal outputted via the signal line 51 is given to the register 103. In the second time, a shift control signal corresponding to a shift vector for which an evaluation function value is to be obtained next is applied, and the corresponding evaluation function value is obtained by the calculation units 92 to 94 and applied to the comparison unit 100. The comparator 100 compares the second calculation result (that is, the calculation result for the second input shift control signal) provided via signal lines 95 to 97 with the first calculation result input from the register 102 via signal line 98. A comparison is made with the minimum value detected the first time (the shift vector indicating the first minimum value is also input from the register 103 via the signal line 99). Therefore, from the second time onwards, the evaluation function values input via the signal lines 95 to 97 and 98 are compared and read until the final result at that stage is obtained. Note that there is no signal input from the signal line 98 at the first time, but if the register 102 is forcibly set to the maximum value that the evaluation function can take, the signal line 98 will be input at the first time. The value input via 98 will never be the minimum value.

Next, the operations of the calculation units 92 to 94 will be explained with reference to FIG. However, since the operations of the calculation units 92 to 94 are exactly the same, only the calculation unit 92 will be described. In addition, in the arithmetic unit 92, parallel processing is performed by the number of lines corresponding to the vertical block size (here, 4 lines are shown), so that the signal line ₄₆₁ in FIG. We will only explain the lineage leading to .

The current frame signal input from the signal line 45 ₁ and the shifted previous frame signal input via the signal line 46 ₁ are subtracted in the subtracter 110 ₁ , and the difference signal is provided to the threshold determination circuit 111 ₁ . It will be done. The threshold determination circuit 111 ₁ determines whether the absolute value of the input difference signal exceeds a certain threshold, and if it does, increments the counter 112 ₁ by one. However, the counter is cleared at the start of motion detection at each stage (if the detection at each stage is divided into multiple stages, this can be read as at the start of each stage of detection). At the end of each stage of motion detection, the values of the counters 112 ₁ to 112 ₄ are read out and input to the adder 113, and the values are input to the signal line 4.
The calculation results of the four systems starting from 6 ₁ to 46 ₄ are summed and output to the signal line 95 .

Note that in the above explanation, the motion detection evaluation function is
In some cases, the evaluation function is "the number of signals whose absolute value exceeds a certain threshold value," but when the evaluation function is "the sum of the absolute values of the difference signals," the determination circuits 111 ₁ to 111 ₄ are Replaced with an absolute value circuit, that is, a circuit that outputs the absolute value of the input, and counter 1
12 ₁ to 112 ₄ may be replaced with adders and registers. In addition, the evaluation function is "sum of squares of difference signals"
In this case, the determination circuits 111 ₁ to 111 ₄ may be replaced with square circuits, that is, circuits that output the square of the input signal, and the counters 112 ₁ to 112 ₄ may be replaced with adders and registers.

Next, the comparing section 100 will be explained with reference to FIG. Although FIG. 10 shows a case where the output signals of four arithmetic units and the shift control signals corresponding to each are input, the configuration can be made in the same manner even when the number of input signals is other.

First, the calculation results of the arithmetic unit input via signal lines 95 and 96 are sent to the comparator 120 and the multiplexer (hereinafter abbreviated as "MPX"), respectively.
122. Comparator 120 is connected to signal line 95
and the signal value on the signal line 96, and if the signal value on the signal line 95 is smaller, the MPX122
output the value of the signal line 95 to the signal line 135 through the signal line 125; otherwise, the value of the signal line 95 is output to the signal line 135.
Output the value of 6. On the other hand, the signal on signal line 125 is also connected to MPX132, and signal line 95
If the value of is smaller, connect signal line 9 to MPX132.
The shift control signal of the signal line 53 corresponding to the value of 5 is output to the signal line 137, otherwise the shift control signal of the signal line 53 is output to the signal line 9.
A shift control signal of the signal line 54 corresponding to the value of 6 is output.

Comparator 121, MPX123 and MPX133
Exactly the same thing is done for signal lines 97 and 98 depending on the magnitude relationship between the values of signal lines 97 and 98.
and 98, the smaller value is output to the signal line 136, and the shift control signal corresponding to the smaller value is output to the signal line 138.

Further, the values output to signal lines 135 and 136 are input to comparator 124 and MPX 127,
If the value of signal line 135 is smaller, MPX1
34 to the shift control signal of signal line 137 to signal line 5
1, otherwise the signal line 138
output the shift control signal. Also, MPX1
27 outputs the smaller value of signal lines 135 and 136 to signal line 101.

As described above, in the present invention, the amount of calculation required for motion detection can be significantly reduced by dividing the motion of a television image into multiple stages.
It is possible to realize an interframe encoding device that follows motion without increasing the device scale.

In addition to the above explanation, the following modifications may also be considered. In the above explanation, each stage (Lth
In the motion detection in stages (L: a finite positive integer), the shift vector with the minimum evaluation function value (that is, one) is detected from the L-th shift vector group, and from this shift vector, the (L
+1) The (L-th) target of motion detection in step
Although the explanation has been made assuming that the shift vector of (for example, two shift vectors in sequence), and the (L+1)th shift vector may be determined from the plurality of shift vectors. In this case, a plurality of shift control signals (signal line 51) are output from the detector 43.

In addition, in the above explanation, the motion vector of the TV image is detected between the input TV signal and the TV signal one frame before, and motion correction is performed. Even if the motion vector is detected between the TV signal and the input TV signal (assumed to be 0.5 frame before), it can be realized with almost the same configuration (however, the capacity of the frame memory of the encoder and decoder will differ). .

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an interframe coding method that follows motion. 2. FIGS. 1 to 3 are diagrams for explaining image motion detection in the present invention, and FIGS. 3 and 4 are block diagrams of an interframe coding/decoding apparatus showing an embodiment of the present invention. 3 and 4, 3...Delay circuit, 5...Subtractor, 7...Quantizer, 9, 18...
... Encoder, 11 ... Prediction signal generation section, 14 ... Frame memory, 17 ... Adder, 20 ... Multiplexer, 22 ... Transmission side buffer memory, 24
. . . receiving buffer memory, 26 . . . demultiplexer, 29 . . . adder, 32 . . . frame memory, 34 . FIGS. 5 to 10 are diagrams showing the components used in the embodiment of the present invention.

Claims (1)

[Claims] 1. An interframe coding device that divides one frame of an input television (TV) signal into a plurality of blocks, detects the motion (motion vector) of a TV image for each block, and performs motion compensation. In this step, an evaluation function value is obtained from the input TV signal and the TV signal of the previous frame (or field) at a position shifted by an arbitrary vector (shift vector) with respect to the same position on the TV screen as the block of the input TV signal. and means for detecting the motion vector by N
It is divided into stages (N≧2) and the Lth stage (L=1,
2,...,N-1), the (L+1)th shift vector group is determined based on the evaluation function value obtained for the determined Lth shift vector group, and in the Nth step, the determined Nth shift vector group is determined. 1 based on the evaluation function value obtained for the shift vector group.
What is claimed is: 1. An interframe encoding device for performing motion correction, comprising: means for detecting shift vectors as motion vectors; and means for encoding the motion vectors. 2. Claim 1, wherein the evaluation function is the number of signals in which a difference signal between the input television signal and a TV signal of a previous frame (or field) at a position shifted by an arbitrary shift vector exceeds a certain threshold value. The interframe encoding device described above.