JPS6320201U - - Google Patents
Info
- Publication number
- JPS6320201U JPS6320201U JP11395286U JP11395286U JPS6320201U JP S6320201 U JPS6320201 U JP S6320201U JP 11395286 U JP11395286 U JP 11395286U JP 11395286 U JP11395286 U JP 11395286U JP S6320201 U JPS6320201 U JP S6320201U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- digital signal
- voltage level
- surge absorber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Safety Devices In Control Systems (AREA)
Description
第１図は本考案に係るデジタル入力の誤入力防
止装置の一実施例を示すブロツク図である。
１０……外部シーケンス回路、２０……デジタ
ル処理装置、３０……誤入力防止装置、３１……
電圧判別回路、３２……サージ吸収器、３３……
入力電圧表示回路、３４Ａ〜３４Ｃ……電圧別表
示灯、３５……出力電圧選択回路、３５Ａ……ピ
ンボード、３６……出力指令回路、３６Ａ……ス
イツチ。
FIG. 1 is a block diagram showing an embodiment of an erroneous input prevention device for digital input according to the present invention. 10... External sequence circuit, 20... Digital processing device, 30... Erroneous input prevention device, 31...
Voltage discrimination circuit, 32... Surge absorber, 33...
Input voltage display circuit, 34A to 34C... Indicator lamp for each voltage, 35... Output voltage selection circuit, 35A... Pin board, 36... Output command circuit, 36A... Switch.
Claims (1)
るサージ吸収器と、このサージ吸収器を通したデ
ジタル信号の電圧レベルを判別する電圧判別回路
と、この電圧判別回路の判別結果を表示する表示
手段と、前記サージ吸収器を通したデジタル信号
の電圧レベルを、予め設定された複数の電圧レベ
ルの中から選択された電圧レベルに変換する出力
電圧選択回路と、この出力電圧選択回路における
電圧レベルを選択する選択手段と、前記出力電圧
選択回路よりのデジタル信号を、スイツチの操作
によりデジタル処理装置へ送出する出力指令回路
とを有してなることを特徴とするデジタル入力の
誤入力防止装置。 a surge absorber that absorbs a surge of a digital signal from an external circuit, a voltage discrimination circuit that discriminates the voltage level of the digital signal that has passed through the surge absorber, and a display means that displays the discrimination result of the voltage discrimination circuit; an output voltage selection circuit that converts the voltage level of the digital signal passed through the surge absorber into a voltage level selected from a plurality of preset voltage levels; and a voltage level in the output voltage selection circuit is selected. 1. An erroneous input prevention device for digital input, comprising a selection means and an output command circuit that sends a digital signal from the output voltage selection circuit to a digital processing device by operating a switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11395286U JPS6320201U (en) | 1986-07-24 | 1986-07-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11395286U JPS6320201U (en) | 1986-07-24 | 1986-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320201U true JPS6320201U (en) | 1988-02-10 |
Family
ID=30996239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11395286U Pending JPS6320201U (en) | 1986-07-24 | 1986-07-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320201U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175630U (en) * | 1988-05-26 | 1989-12-14 |
-
1986
- 1986-07-24 JP JP11395286U patent/JPS6320201U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175630U (en) * | 1988-05-26 | 1989-12-14 |
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