JPS6320247U - - Google Patents
Info
- Publication number
- JPS6320247U JPS6320247U JP11080786U JP11080786U JPS6320247U JP S6320247 U JPS6320247 U JP S6320247U JP 11080786 U JP11080786 U JP 11080786U JP 11080786 U JP11080786 U JP 11080786U JP S6320247 U JPS6320247 U JP S6320247U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- control unit
- processing device
- data processing
- arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案のデータ処理装置におけるメモ
リアクセス機構の概略図。第２図は同じ配列を有
するデータ対、｛Ｘ（ｎ）｝、｛Ｙ（ｎ）｝のメ
モリへの格納図。第３図は倍長のデータのメモリ
への格納図。
１……制御部、２……アドレスポインタ、３…
…メモリＡ、４……メモリＢ、５……演算部。
FIG. 1 is a schematic diagram of a memory access mechanism in a data processing device of the present invention. FIG. 2 is a storage diagram of a data pair {X(n)} and {Y(n)} having the same arrangement in memory. FIG. 3 is a diagram showing how double-length data is stored in memory. 1...Control unit, 2...Address pointer, 3...
...Memory A, 4...Memory B, 5...Arithmetic section.
Claims (1)
を有するデータ処理装置において、該メモリ制御
部中の１つのアドレスポインタに対して複数のメ
モリバンクを有し、該メモリバンクに対してそれ
ぞれ独立に、リードライトを行なう手段を設けた
メモリアクセス機構を備えてなるデータ処理装置
。 A data processing device including a memory, a memory control unit, an arithmetic unit, and an arithmetic control unit, which has a plurality of memory banks for one address pointer in the memory control unit, and for each memory bank independently, A data processing device comprising a memory access mechanism provided with means for reading and writing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11080786U JPS6320247U (en) | 1986-07-18 | 1986-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11080786U JPS6320247U (en) | 1986-07-18 | 1986-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320247U true JPS6320247U (en) | 1988-02-10 |
Family
ID=30990150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11080786U Pending JPS6320247U (en) | 1986-07-18 | 1986-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320247U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5129846A (en) * | 1974-09-06 | 1976-03-13 | Tokyo Shibaura Electric Co | |
| JPS5555489A (en) * | 1978-10-19 | 1980-04-23 | Sanyo Electric Co Ltd | Data processing system |
| JPS57105078A (en) * | 1980-12-23 | 1982-06-30 | Hitachi Ltd | Vector processor |
| JPS5968068A (en) * | 1982-10-12 | 1984-04-17 | Nec Corp | Memory board |
-
1986
- 1986-07-18 JP JP11080786U patent/JPS6320247U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5129846A (en) * | 1974-09-06 | 1976-03-13 | Tokyo Shibaura Electric Co | |
| JPS5555489A (en) * | 1978-10-19 | 1980-04-23 | Sanyo Electric Co Ltd | Data processing system |
| JPS57105078A (en) * | 1980-12-23 | 1982-06-30 | Hitachi Ltd | Vector processor |
| JPS5968068A (en) * | 1982-10-12 | 1984-04-17 | Nec Corp | Memory board |
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