JPS6321121Y2 - - Google Patents

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Publication number
JPS6321121Y2
JPS6321121Y2 JP1981185250U JP18525081U JPS6321121Y2 JP S6321121 Y2 JPS6321121 Y2 JP S6321121Y2 JP 1981185250 U JP1981185250 U JP 1981185250U JP 18525081 U JP18525081 U JP 18525081U JP S6321121 Y2 JPS6321121 Y2 JP S6321121Y2
Authority
JP
Japan
Prior art keywords
thyristor
switching means
resistor
motor
predetermined time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981185250U
Other languages
Japanese (ja)
Other versions
JPS5890001U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981185250U priority Critical patent/JPS5890001U/en
Publication of JPS5890001U publication Critical patent/JPS5890001U/en
Application granted granted Critical
Publication of JPS6321121Y2 publication Critical patent/JPS6321121Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B60VEHICLES IN GENERAL
    • B60LPROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L3/00Electric devices on electrically-propelled vehicles for safety purposes; Monitoring operating variables, e.g. speed, deceleration or energy consumption
    • B60L3/08Means for preventing excessive speed of the vehicle
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B60VEHICLES IN GENERAL
    • B60LPROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L15/00Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles
    • B60L15/10Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles for automatic control superimposed on human control to limit the acceleration of the vehicle, e.g. to prevent excessive motor current
    • B60L15/12Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles for automatic control superimposed on human control to limit the acceleration of the vehicle, e.g. to prevent excessive motor current with circuits controlled by relays or contactors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B60VEHICLES IN GENERAL
    • B60LPROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L50/00Electric propulsion with power supplied within the vehicle
    • B60L50/50Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells
    • B60L50/52Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells characterised by DC-motors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02TCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00Road transport of goods or passengers
    • Y02T10/60Other road transportation technologies with climate change mitigation effect
    • Y02T10/64Electric machine technologies in electromobility
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02TCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00Road transport of goods or passengers
    • Y02T10/60Other road transportation technologies with climate change mitigation effect
    • Y02T10/70Energy storage systems for electromobility, e.g. batteries
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02TCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00Road transport of goods or passengers
    • Y02T10/60Other road transportation technologies with climate change mitigation effect
    • Y02T10/72Electric energy management in electromobility

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Transportation (AREA)
  • Mechanical Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)

Description

【考案の詳細な説明】 この考案は電気自動車の速度制御装置の動作異
常検出回路に関し、特に電気自動車の速度を制御
するための複数段のスイツチング素子が異常であ
ることを判別する動作異常検出回路に関する。
[Detailed description of the invention] This invention relates to an operation abnormality detection circuit for a speed control device for an electric vehicle, and in particular an operation abnormality detection circuit that determines whether a multi-stage switching element for controlling the speed of an electric vehicle is abnormal. Regarding.

第1図はこの考案の背景となりかつこの考案に
適用される電気自動車の速度制御回路10の回路
図である。図において、複数個の蓄電池11には
メインスイツチ12と抵抗13,14とスイツチ
15とモータ16とが直列接続される。メインス
イツチ12は電気自動車のキースイツチ(図示せ
ず)と連動する。スイツチ15は、アクセル(図
示せず)が操作されたことに応じて閉成してモー
タ16に電力を供給する。抵抗13には第1のス
イツチング手段の一例のサイリスタ17が並列接
続される。サイリスタ17はスイツチ15の閉成
時から少なくとも所定の時間を経過した後に開成
することによつて抵抗13の両端を短絡させる。
換言すれば、電気自動車はスイツチ15の閉成時
から少なくともある時間を経過するまでにアクセ
ルが踏み込まれても低速で走行する。抵抗13,
14には第2のスイツチング手段の一例のサイリ
スタ18が並列接続される。同様に、サイリスタ
18はサイリスタ17の導通開始時から少なくと
も所定時間Tを経た後に導通することによつて抵
抗13,14を短絡させる。換言すれば、電気自
動車はサイリスタ17の導通開始時から少なくと
も所定時間Tを経過するまでにアクセルが踏み込
まれても中速で走行する。サイリスタ17,18
にはゲート信号発生回路(図示せず)から上述の
ように少なくとも各所定時間を経た後に自動的に
あるいはアクセル操作に応じてゲート信号が与え
られる。
FIG. 1 is a circuit diagram of a speed control circuit 10 for an electric vehicle that forms the background of this invention and is applied to this invention. In the figure, a main switch 12, resistors 13 and 14, a switch 15, and a motor 16 are connected in series to a plurality of storage batteries 11. The main switch 12 is linked to a key switch (not shown) of the electric vehicle. The switch 15 closes and supplies power to the motor 16 in response to operation of an accelerator (not shown). A thyristor 17, which is an example of first switching means, is connected in parallel to the resistor 13. The thyristor 17 short-circuits both ends of the resistor 13 by opening it after at least a predetermined time has elapsed since the switch 15 was closed.
In other words, the electric vehicle runs at a low speed even if the accelerator is depressed until at least a certain amount of time has elapsed since the switch 15 was closed. Resistance 13,
A thyristor 18, which is an example of second switching means, is connected in parallel to 14. Similarly, the thyristor 18 shorts out the resistors 13 and 14 by becoming conductive after at least a predetermined time T has elapsed since the thyristor 17 started being conductive. In other words, the electric vehicle runs at medium speed even if the accelerator is depressed until at least the predetermined time T has elapsed since the thyristor 17 started conducting. Thyristor 17, 18
As described above, a gate signal is applied from a gate signal generation circuit (not shown) automatically or in response to an accelerator operation after at least each predetermined time period.

動作において、キースイツチが操作されると、
メインスイツチ12は閉成される。続いて、アク
セルが踏み込まれると、スイツチ15は閉成され
る。応じて、モータ16には抵抗13,14で降
圧された蓄電池11の電圧が印加される。このた
め、電気自動車は低速で走行する。スイツチ15
の閉成時から決められたある時間が経過した後に
アクセルが踏み込まれるとあるいは踏み込まれて
いるとサイリスタ17が導通して抵抗13を短絡
させるので、モータ16には抵抗14のみで降圧
された蓄電池11の電圧が印加される。このた
め、電気自動車は中速で走行する。続いて、サイ
リスタ17の導通開始時から所定時間Tが経過し
た後にアクセルが更に踏み込まれるとサイリスタ
18が導通して抵抗13,14を短絡させるの
で、モータ16には蓄電池11の電圧が直接印加
される。応じて、電気自動車は高速で走行する。
In operation, when the key switch is operated,
Main switch 12 is closed. Subsequently, when the accelerator is depressed, the switch 15 is closed. Accordingly, the voltage of the storage battery 11, which has been stepped down by the resistors 13 and 14, is applied to the motor 16. For this reason, electric vehicles run at low speeds. switch 15
When the accelerator is depressed or is being depressed after a predetermined time has elapsed since the closing of the thyristor 17, the thyristor 17 becomes conductive and short-circuits the resistor 13. 11 voltages are applied. Therefore, electric vehicles run at medium speeds. Subsequently, when the accelerator is further depressed after a predetermined time T has elapsed since the thyristor 17 started conducting, the thyristor 18 becomes conductive and short-circuits the resistors 13 and 14, so that the voltage of the storage battery 11 is directly applied to the motor 16. Ru. Accordingly, the electric vehicle travels at high speed.

しかし、上述のような回路では、たとえばサイ
リスタ17が断線破壊をしたり、またはゲート回
路の異常で点弧しないと、サイリスタ18の点弧
によつて抵抗13,14が一度に短絡されてしま
うため、モータ16に過大な電流が流れて発熱し
たり、乗客に大きなシヨツクを与えることにな
る。このため、上述のような現象が起こつたとと
きには、それを検出してユーザに修理等を促すこ
とが望まれる。
However, in the above-described circuit, if the thyristor 17 fails to fire due to breakage, for example, or an abnormality in the gate circuit, the resistors 13 and 14 will be short-circuited at once due to the firing of the thyristor 18. , an excessive current flows through the motor 16, causing heat generation and giving a large shock to the passengers. Therefore, when the above-mentioned phenomenon occurs, it is desirable to detect it and prompt the user to repair the device.

そこで、各スイツチング素子が正常であるかを
検出する方法としては、各スイツチング素子と並
列接続された各抵抗の両端(図示では接続点イ点
とロ点およびイ点とハ点またはロ点とハ点)の電
位差を検出することが考えられる。すなわち、こ
の検出方法は、スイツチ15を閉成させたとき抵
抗13,14の両端のイ点とロ点またはイ点とハ
点の電位差が大きくなり、サイリスタ17,18
を導通させたときイ点とロ点またはイ点とハ点の
電位差が小さくなることを利用したものである。
Therefore, the method of detecting whether each switching element is normal is to detect whether the switching element is connected in parallel with both ends of each resistor (in the figure, the connection points A and B, and between A and C, or between B and H). It is conceivable to detect the potential difference between points). That is, in this detection method, when the switch 15 is closed, the potential difference between points A and B or between points A and C on both ends of the resistors 13 and 14 becomes large, and the thyristors 17 and 18
This takes advantage of the fact that when conductive, the potential difference between points A and B or between points A and C becomes smaller.

ところが、この検出方法は、スイツチング素子
が1段の場合であればその動作状態を検出できる
が、スイツチング素止が2段の場合には初段のス
イツチング素子の動作状態を検出できない。その
理由は、サイリスタ17が異常であつてもサイリ
スタ18が導通すると、イ点とロ点の電位差も低
下させてしまうので、見かけ上サイリスタ17も
正常であることを検出するためである。
However, this detection method can detect the operating state of a single stage switching element, but cannot detect the operating state of the first stage switching element when there are two switching elements. The reason for this is that even if thyristor 17 is abnormal, if thyristor 18 becomes conductive, the potential difference between point A and point B also decreases, so it is detected that thyristor 17 is also apparently normal.

それゆえに、この考案の目的は、安価でかつ簡
単な回路構成で、速度制御回路における複数段の
各スイツチング素子が異常であることを容易に検
出できる動作異常検出回路を提供することであ
る。
Therefore, an object of the present invention is to provide an operation abnormality detection circuit that is inexpensive and has a simple circuit configuration and can easily detect abnormality in each switching element in a plurality of stages in a speed control circuit.

この考案を要約すれば、少なくとも第1の抵抗
に並列接続された第1のスイツチング手段の導通
状態を検出する第1の検出手段と、直列接続され
た少なくとも第1および第2の抵抗に並列接続さ
れた第2のスイツチング手段の導通状態を検出す
る第2の検出手段を設け、遅延手段によつて第1
の検出手段出力を所定時間より短い予め定める時
間だけ遅延させ、第2の検出手段出力があつた後
に遅延手段出力が入力されたことに基づいて、第
1のスイツチング手段の異常を判別するようにし
たものである。
To summarize this invention, first detection means detects the conduction state of the first switching means connected in parallel to at least a first resistor, and at least first and second resistors connected in series are connected in parallel. A second detection means is provided for detecting the conduction state of the second switching means, and the delay means detects the conduction state of the second switching means.
The output of the first switching means is delayed by a predetermined time shorter than the predetermined time, and an abnormality of the first switching means is determined based on the fact that the output of the delay means is input after the output of the second detection means is received. This is what I did.

以下に、図面を参照してこの考案の一実施例に
ついて説明する。
An embodiment of this invention will be described below with reference to the drawings.

第2図はこの考案の一実施例の動作異常検出回
路20のブロツク図である。構成において、第1
の検出手段の一例の導通状態検出回路21は、サ
イリスタ17の導通状態を検出するものであり、
サイリスタ17と並列接続された抵抗13の両端
イ点とロ点の電位差が0になつたことに応じて出
力信号を遅延回路23に与える。遅延回路23
は、検出回路21からの出力信号をサイリスタ1
7の導通開始時からサイリスタ18が導通するま
で最低限確保された所定時間Tより短い予め定め
た時間T1だけ遅延させ、その出力信号を順序判
別回路24の一例のD形フリツプフロツプ241
のクロツク端子(図示ではCLである)に与える。
第2の検出手段の一例の導通状態検出回路22
は、サイリスタ18の導通状態を検出するもので
あり、サイリスタ18と並列接続された抵抗1
3,14の両端イ点とハ点の電位差が0になつた
ことに応じて出力信号をD形フリツプフロツプ2
41のデータ端子(図示ではDである)に与え
る。
FIG. 2 is a block diagram of an operational abnormality detection circuit 20 according to an embodiment of this invention. In the configuration, the first
The conduction state detection circuit 21, which is an example of the detection means, detects the conduction state of the thyristor 17,
An output signal is given to the delay circuit 23 in response to the potential difference between a point A and a point L at both ends of the resistor 13 connected in parallel with the thyristor 17 becoming zero. Delay circuit 23
is the output signal from the detection circuit 21 to the thyristor 1.
The D-type flip-flop 241, which is an example of the order discriminating circuit 24, delays the output signal from the D-type flip-flop 241, which is an example of the order discriminating circuit 24, by a predetermined time T1 shorter than the minimum predetermined time T from the start of conduction of the thyristor 7 until the thyristor 18 becomes conductive.
to the clock terminal (CL in the illustration).
Continuity state detection circuit 22 as an example of second detection means
is for detecting the conduction state of the thyristor 18, and the resistor 1 connected in parallel with the thyristor 18
In response to the potential difference between points A and C at both ends of 3 and 14 becoming 0, the output signal is sent to the D-type flip-flop 2.
41 data terminal (D in the illustration).

なお、順序判別回路24は入力信号の順序を判
別できるその他の各種のフリツプフロツプやその
他の論理回路などを使用してもよい。
Note that the order determining circuit 24 may use other types of flip-flops or other logic circuits that can determine the order of input signals.

ここで、動作異常検出回路20を上述のように
構成した理由について述べる。これは、速度制御
回路10がサイリスタ17の点弧信号発生時から
少なくとも所定時間Tを経過した後でないとサイ
リスタ18の点弧信号が発生しないように定めら
れているためである。すなわち、サイリスタ1
7,18およびゲート信号発生回路が正常な場合
はイ点とロ点の電位差の低下およびロ点とハ点の
電位差の低下に少なくとも時間Tに相当するずれ
を生ずるのに対し、サイリスタ17が異常な場合
はイ点とロ点の電位差の低下およびロ点とハ点の
電位差の低下に時間的なずれを生じないことを利
用するためである。また、他の理由としては、フ
リツプフロツプを利用した通常の順序判別回路で
各両端における電位差の発生順序を判別する際に
電位差の発生順序が同時の場合に判別できないた
めである。
Here, the reason why the abnormality detection circuit 20 is configured as described above will be described. This is because the speed control circuit 10 is designed not to generate the firing signal for the thyristor 18 until at least a predetermined time T has elapsed since the firing signal for the thyristor 17 was generated. That is, thyristor 1
If 7, 18 and the gate signal generation circuit are normal, there will be a lag corresponding to at least time T in the decrease in the potential difference between points A and B and the decrease in the potential difference between points B and C, but if thyristor 17 is abnormal. This is to take advantage of the fact that in this case, there is no time lag in the decrease in the potential difference between points A and B and between points B and C. Another reason is that a normal order determining circuit using a flip-flop cannot determine the order in which the potential differences occur at both ends when the order in which the potential differences occur is the same.

第3図はこの実施例の動作異常検出回路20の
各部の出力波形図を示し、特に実線はサイリスタ
17,18の正常時の出力波形図であり、点線は
サイリスタ17の異常時の出力波形図である。
FIG. 3 shows an output waveform diagram of each part of the operational abnormality detection circuit 20 of this embodiment. In particular, the solid line is the output waveform diagram of the thyristors 17 and 18 when the thyristors 17 and 18 are normal, and the dotted line is the output waveform diagram of the thyristor 17 when the thyristor 17 is abnormal. It is.

次に、第1図ないし第3図を参照してこの実施
例の動作を説明する。なお、以下の設明ではアク
セルペダルが十分に踏み込まれているものとす
る。まず、サイリスタ17,18が正常な場合に
ついて説明する。この場合は、メインスイツチ1
2およびスイツチ15が閉成されると、モータ1
6に抵抗13,14で降圧された蓄電池11の電
圧が印加される。そして、スイツチ15の閉成時
から決められたある時間が経過した時刻t1にな
ると、サイリスタ17は導通状態となる。応じ
て、モータ16には抵抗14で降圧された蓄電池
11の電圧が印加される。このとき、イ点とロ点
の電位差がほぼ0であるため、検出回路21は時
刻t1にサイリスタ17の導通状態を検出した出
力信号を遅延回路23に与える。遅延回路23
は、検出回路21の出力信号をサイリスタ17の
導通開始時の時刻t1からサイリスタ18が導通
する時刻t2までの所定時間Tより短い予め定め
た時間T1だけ遅延させ、その出力信号をD形フ
リツプフロツプ241のCL端子に与える。続い
て、サイリスタ17の点弧時t1から所定時間T
後の時刻t2になると、サイリスタ18は導通状
態となる。応じて、モータ16には蓄電池11の
電圧が印加される。このとき、イ点とハ点の電位
差がほぼ0であるため、検出回路22は時刻t2
にサイリスタ18の導通状態を検出した出力信号
をD形フリツプフロツプ241のD端子に与え
る。このため、D形フリツプフロツプ241は、
遅延回路23の出力信号があつた後に検出回路2
2の出力信号が入力されるので、サイリスタ1
7,18が正常であることを判別する。
Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 3. In addition, in the following setup, it is assumed that the accelerator pedal is fully depressed. First, a case where the thyristors 17 and 18 are normal will be described. In this case, main switch 1
2 and switch 15 are closed, motor 1
The voltage of the storage battery 11, which has been stepped down by resistors 13 and 14, is applied to 6. Then, at time t1, when a predetermined period of time has elapsed since the switch 15 was closed, the thyristor 17 becomes conductive. Accordingly, the voltage of the storage battery 11 , which has been stepped down by the resistor 14 , is applied to the motor 16 . At this time, since the potential difference between point A and point L is approximately 0, the detection circuit 21 provides an output signal detecting the conduction state of the thyristor 17 to the delay circuit 23 at time t1. Delay circuit 23
The output signal of the detection circuit 21 is delayed by a predetermined time T1 shorter than the predetermined time T from the time t1 when the thyristor 17 starts conducting to the time t2 when the thyristor 18 becomes conductive, and the output signal is sent to the D-type flip-flop 241. to the CL terminal of. Subsequently, a predetermined time T is elapsed from the firing time t1 of the thyristor 17.
At later time t2, the thyristor 18 becomes conductive. Accordingly, the voltage of the storage battery 11 is applied to the motor 16 . At this time, since the potential difference between point A and point C is almost 0, the detection circuit 22 detects the voltage at time t2.
Then, an output signal that detects the conduction state of the thyristor 18 is applied to the D terminal of the D-type flip-flop 241. Therefore, the D-type flip-flop 241 is
After the output signal of the delay circuit 23 is received, the detection circuit 2
Since the output signal of thyristor 2 is input, thyristor 1
7 and 18 are determined to be normal.

次に、サイリスタ17が異常の場合について説
明する。この場合は、メインスイツチ12および
スイツチ15が閉成されると、モータに抵抗1
3,14で降圧された蓄電池11の電圧が印加さ
れる。そして、時刻t1になつても、サイリスタ
17は異常であるため導通しない。応じて、時刻
t1においてもモータ16に抵抗13,14で降
圧された蓄電池11の電圧が印加されるので、イ
点とロ点の電位差は0とならない。このため、検
出回路21は時刻t1にサイリスタ17の導通状
態を検出した出力信号を遅延回路23に与えな
い。続いて、時刻t2になると、サイリスタ18
は導通状態となる。応じて、モータ16には蓄電
池11の電圧が直接印加される。このとき、イ点
とハ点の電位差がほぼ0であるため、検出回路2
2は時刻t2にサイリスタ18の導通状態を検出
した出力信号をD形フリツプフロツプ241のD
端子に与える。また、イ点とロ点の電位差および
ロ点とハ点の電位差が同時にほぼ0となるので、
検出回路21は時刻t2にサイリスタ17の導通
状態を検出した出力信号を遅延回路23に与え
る。遅延回路23は、検出回路21の検出信号を
サイリスタ18の導通開始時の時刻t2から予め
定めた時間T1だけ遅延させ、その出力信号をD
形フリツプフロツプ241のCL端子に与える。
このため、D形フリツプフロツプ241は、検出
回路22の出力信号があつた後に遅延回路23の
出力信号が入力されるので、サイリスタ17の異
常を判別し、時刻t2から時間T1後に出力か
らハイレベルの異常信号を導出する。
Next, a case where the thyristor 17 is abnormal will be described. In this case, when the main switch 12 and switch 15 are closed, the motor is
3 and 14, the voltage of the storage battery 11 is applied. Then, even at time t1, the thyristor 17 is not conductive because it is abnormal. Accordingly, the voltage of the storage battery 11, which has been stepped down by the resistors 13 and 14, is applied to the motor 16 at time t1 as well, so the potential difference between points A and B does not become zero. Therefore, the detection circuit 21 does not provide the delay circuit 23 with an output signal that detects the conduction state of the thyristor 17 at time t1. Subsequently, at time t2, the thyristor 18
becomes conductive. Accordingly, the voltage of the storage battery 11 is directly applied to the motor 16 . At this time, since the potential difference between point A and point C is almost 0, the detection circuit 2
2 outputs the output signal that detects the conduction state of the thyristor 18 at time t2 to the D flip-flop 241.
Give it to the terminal. Also, since the potential difference between points A and B and the potential difference between points B and C become almost 0 at the same time,
The detection circuit 21 provides an output signal that detects the conduction state of the thyristor 17 to the delay circuit 23 at time t2. The delay circuit 23 delays the detection signal of the detection circuit 21 by a predetermined time T1 from the time t2 when the thyristor 18 starts conducting, and outputs the output signal to D.
It is applied to the CL terminal of the flip-flop 241.
Therefore, since the output signal of the delay circuit 23 is inputted to the D-type flip-flop 241 after the output signal of the detection circuit 22 is received, the D-type flip-flop 241 determines whether there is an abnormality in the thyristor 17 and changes the output to a high level after time T1 from time t2. Derive an abnormal signal.

ところで、D形フリツプフロツプ241から導
出された異常信号は、表示器または警報器などに
与えてユーザに知らせるようにしてもよい。
Incidentally, the abnormality signal derived from the D-type flip-flop 241 may be provided to a display or an alarm to inform the user.

なお、上述の実施例では、検出回路21の出力
信号のみを遅延させた場合について説明したが、
これに限らず検出回路22の出力信号を遅延させ
て利用してもよい。この場合は、検出回路22の
出力信号の遅延させる時間をT2とすると、遅延
時間T1と所定時間Tとの関係が第1式の関係に
選ばれる。
In addition, in the above-mentioned embodiment, the case where only the output signal of the detection circuit 21 was delayed was explained.
The present invention is not limited to this, and the output signal of the detection circuit 22 may be delayed and used. In this case, assuming that the time for delaying the output signal of the detection circuit 22 is T2, the relationship between the delay time T1 and the predetermined time T is selected to be the relationship of the first equation.

T1−T2<T …(1) また、上述の実施例では、速度制御回路におけ
るスイツチング素子が2つの場合について説明し
たが、これに限らずスイツチング素子を3つ使用
した場合にも利用できる。この場合は、1段目か
ら3段目のスイツチング素子の導通状態を検出し
た検出信号をa,b,cとするとともに、検出信
号a,b,cの遅延時間をTa,Tb,Tc、検出
信号aとbとの時間間隔をTab、検出信号bとc
との時間間隔をTbcとすると、それぞれの時間関
係が第2式ないし第4式の関係に選ばれる。
T1-T2<T (1) Furthermore, in the above-described embodiment, the case where the number of switching elements in the speed control circuit is two was explained, but the present invention is not limited to this, and the present invention can also be used in a case where three switching elements are used. In this case, the detection signals that detect the conduction states of the switching elements in the first to third stages are a, b, and c, and the delay times of the detection signals a, b, and c are Ta, Tb, Tc, and detection Tab is the time interval between signals a and b, and detection signals b and c are
Let Tbc be the time interval, then the respective time relationships are selected as the relationships of the second to fourth equations.

Ta<Tb<Tc …(2) Ta−Tb<Tab …(3) Tb−Tc<Tbc …(4) さらに、上述の実施例では、動作異常検出回路
を電気自動車に搭載した場合について説明した
が、これに限らずたとえば整備工場またはユーザ
の車庫などに設けて定期点検時や始動点検時に用
いるようにしてもよい。
Ta<Tb<Tc …(2) Ta−Tb<Tab …(3) Tb−Tc<Tbc …(4) Furthermore, in the above embodiment, the case where the operational abnormality detection circuit is installed in an electric vehicle was explained. However, the present invention is not limited to this, and it may be installed in a maintenance shop or a user's garage, for example, and used during periodic inspections or startup inspections.

以上のように、この考案によれば、少なくとも
第1の抵抗に並列接続された第1のスイツチング
手段の導通状態を検出する第1の検出手段と、そ
れぞれが直列接続された少なくとも第1および第
2の抵抗に並列接続された第2のスイツチング手
段の導通状態を検出する第2の検出手段を設け、
遅延手段によつて第1の検出手段出力を所定時間
より短い予め定める時間だけ遅延させ、第2の検
出手段出力があつた後に、遅延手段出力が入力さ
れたことに基づいて、第1のスイツチング手段の
異常を判別するようにしたので、比較的簡単な回
路構成で、速度制御における複数段の各スイツチ
ング手段の異常を容易に検出できる。さらに、第
1のスイツチング手段の点弧確認信号が第1のス
イツチング手段によつて生じたものであるかある
いは第2のスイツチング手段によつて生じたもの
であるかを容易に判別できる。
As described above, according to this invention, the first detection means detects the conduction state of the first switching means connected in parallel to at least the first resistor, and the at least first and first switching means connected in series, respectively. a second detection means for detecting the conduction state of the second switching means connected in parallel to the second resistor;
The output of the first detection means is delayed by a predetermined time shorter than the predetermined time by the delay means, and after the output of the second detection means is received, the first switching is performed based on the input of the output of the delay means. Since abnormalities in the means are determined, abnormalities in each of the plurality of stages of switching means in speed control can be easily detected with a relatively simple circuit configuration. Furthermore, it can be easily determined whether the firing confirmation signal of the first switching means is generated by the first switching means or the second switching means.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の背景となりかつこの考案に
適用される電気自動車の速度制御回路10の回路
図である。第2図はこの考案の一実施例の動作異
常検出回路20のブロツク図である。第3図はこ
の実施例の動作異常検出回路20の各部の出力波
形図である。 図において、13,14は抵抗、16はモー
タ、17,18はサイリスタ、21,22は検出
回路、23は遅延回路、241はD形フリツプフ
ロツプを示す。
FIG. 1 is a circuit diagram of a speed control circuit 10 for an electric vehicle that forms the background of this invention and is applied to this invention. FIG. 2 is a block diagram of an operational abnormality detection circuit 20 according to an embodiment of this invention. FIG. 3 is an output waveform diagram of each part of the abnormal operation detection circuit 20 of this embodiment. In the figure, 13 and 14 are resistors, 16 is a motor, 17 and 18 are thyristors, 21 and 22 are detection circuits, 23 is a delay circuit, and 241 is a D-type flip-flop.

Claims (1)

【実用新案登録請求の範囲】 その回転力によつて電気自動車を走行駆動する
ためのモータ、 それぞれが電源と前記モータとの間に直列接続
される少なくとも第1および第2の抵抗、 前記少なくとも第1の抵抗に並列接続され、導
通することによつて前記電気自動車を相対的に低
速度で走行させるのに要する電力を前記電源から
前記モータに供給する第1のスイツチング手段、 前記直列接続された第1および第2の抵抗に並
列接続され、前記第1のスイツチング手段が導通
してから予め定める時間経過後に導通することに
よつて、前記電気自動車を相対的に高速度で走行
させるのに要する電力を前記モータに供給する第
2のスイツチング手段、 前記第1の抵抗の両端の電圧変化に応じて、前
記第1のスイツチング手段の導通状態を検出する
第1の検出手段、 前記第2の抵抗の両端の電圧変化に応じて、前
記第2のスイツチング手段の導通状態を検出する
第2の検出手段、 前記第1の検出手段出力を前記所定時間よりも
短い予め定める時間だけ遅延させる遅延手段、お
よび 前記第2の検出手段出力があつた後に、前記遅
延手段出力が入力されたことに基づいて、前記第
1のスイツチング手段が異常であることを判別す
る異常判別手段を備えた、電気自動車の速度制御
装置の動作異常検出回路。
[Claims for Utility Model Registration] A motor for driving an electric vehicle by its rotational force, at least a first resistor and a second resistor each connected in series between a power source and the motor; a first switching means that is connected in parallel to one of the resistors connected in series, and supplies electric power necessary for running the electric vehicle at a relatively low speed from the power source to the motor by being electrically connected; The first switching means is connected in parallel to the first and second resistors, and is made conductive after a predetermined time has elapsed since the first switching means has been made conductive. a second switching means for supplying electric power to the motor; a first detection means for detecting a conduction state of the first switching means according to a voltage change across the first resistor; and a second resistor. a second detection means for detecting the conduction state of the second switching means in accordance with a voltage change across the second switching means; a delay means for delaying the output of the first detection means by a predetermined time shorter than the predetermined time; and an electric vehicle comprising abnormality determining means for determining that the first switching means is abnormal based on the input of the output of the delay means after the output of the second detection means is received. Abnormal operation detection circuit for speed control equipment.
JP1981185250U 1981-12-12 1981-12-12 Abnormal operation detection circuit for electric vehicle speed control device Granted JPS5890001U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981185250U JPS5890001U (en) 1981-12-12 1981-12-12 Abnormal operation detection circuit for electric vehicle speed control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981185250U JPS5890001U (en) 1981-12-12 1981-12-12 Abnormal operation detection circuit for electric vehicle speed control device

Publications (2)

Publication Number Publication Date
JPS5890001U JPS5890001U (en) 1983-06-18
JPS6321121Y2 true JPS6321121Y2 (en) 1988-06-10

Family

ID=29986132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981185250U Granted JPS5890001U (en) 1981-12-12 1981-12-12 Abnormal operation detection circuit for electric vehicle speed control device

Country Status (1)

Country Link
JP (1) JPS5890001U (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS588671B2 (en) * 1975-02-15 1983-02-17 三菱電機株式会社 Chiyokuryudendoukiseigiyosouchi

Also Published As

Publication number Publication date
JPS5890001U (en) 1983-06-18

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