JPS63220675A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image compression encoding device, and particularly to an image compression device that compresses an image using the MH encoding method.

[Prior art]

MH (Modified Huffman) converts image information into electrical signals by scanning the original image with an optical sensor, etc.
2. Description of the Related Art An image compression device that performs compression using an encoding method is known.

The MH code is a code corresponding to the number of consecutive pixels of the same color (white or black) in image information (run length), and this MH code
In the encoding method, image compression is performed by converting image information into a code string of MH codes.

FIG. 3 shows a block diagram when the operation of a conventional device of this type is realized by hardware. An outline of the operation of the conventional image compression device will be described below. Signal A in Fig. 3 is the image information to be encoded (“H” represents black and “L” represents white), and the image information is the image reading speed (hereinafter referred to as pixel reading period) in scanning of the optical sensor etc. mentioned above. (referred to as t) is input to the run length counting circuit 10 bit serially.

The run length counting circuit 10 counts continuous image information of the same color when it is input. One run length is determined when image information of different colors is input. At this time, the run length counting circuit 10 outputs the run length as a signal B.

Signal B is input to the address line of the ROM 20 that stores the MH code table and the MIT code length, and accesses the MH code and MH code length corresponding to the run length of . The ROM20 outputs the MH code as a signal C to the data output line.
The MT-T code length is also output as a parallel signal as a signal. Since the MH code length of the MH code differs depending on each code,
In order to output the M I-1 code string, the signal C is
It is necessary to extract MH codes of the number of pits indicated by the MH code length of , and fill them in without any gaps. 30 is a well-known hit shifter circuit composed of a multiplexer circuit and a radial circuit, which extracts MI (signs) corresponding to the number of bits indicated by the M H code length of the signal from the signal C and fills them without gaps as a parallel signal E. Perform the operation of outputting to the outside. Image compression was performed by repeating the above operations.

When this method is used, there are drawbacks as described below. That is, the time interval at which the B signal accesses the ROM 20 is the same as the image reading cycle t in the fastest case. Therefore, there is a limit to speeding up when considering the delay time of MI-I code access in the ROM 20.

〔the purpose〕

The present invention has been made in view of the following two points, and an object of the present invention is to provide an image processing device that compresses image information at high speed.

〔Example〕

The present invention will be explained below based on preferred embodiments.

As described above, the MH code is a code corresponding to the number of consecutive pixels of the same color (white or black) (run length) in image information. In addition, M
In other words, there is a make-up code representing run lengths from 64 to 2560, and for run lengths of 63 or less, there is only a termination code, and for run lengths of 64 or more, there is a termination code after the make-up code. Add \1 to make it correspond. However, in this method, the longest run length is the makeup code "2560".
``10 terminus 1 code''63'' for a total of 2623
Since only up to 2623 can be represented, run lengths exceeding 2623 can be handled by adding a make-up code and a termination code after the make-up code "2623".

Therefore, in the MH image compression apparatus, in order to count the run length, the number of consecutive pixels of the same color is counted until pixel information (change point) in which the color changes in the image information is input. Since the value counted until the change point is input is the run length, when the change point is input, the corresponding MH
The sign is determined (hereinafter referred to as the sign is determined).

Here, if the above counting is performed bit by bit, M I corresponding to the run length (code access and M I
If the -T code generation operation is not performed during the period t of the image clock, the image information input bit by bit cannot be processed. Therefore, the image information input bit by bit is converted into n-bit parallel signals, and the above-mentioned run length is counted for each n-bit parallel signal.

For example, consider an n-bit parallel signal output from a parallel shift circuit that receives an n-bit parallel signal every time an image input signal input one bit at a time is shifted by +-t, . . . Then, the n-bit parallel signal is held for a time of nX (image input period t) before being replaced with the n-bit of the new image signal. Therefore, the time required for the above-mentioned run length counting, MH code access operation, and generation operation can be n times longer than when the run length is counted bit by bit.

Therefore, when looking at the image information appearing in the parallel signal n hits, if there is no changing point, the run length is counted by adding n to the counting circuit, and if a changing point is found, the value of the counting circuit is calculated. The basic operation is to access the MH code table using the sum of the number of pixels up to the change point as a run length, and output the corresponding MH code within the time nXt.

However, this method has some problems, which will be described later, and a solution is needed.

First, if there are multiple changing points in the n bits, if all the multiple MH codes determined by these changing points are not output during the nXj time, the image information that is parallel-shifted every nXt time will be In processing, the run length of the sum of the value of the above-mentioned counting circuit and the number of pixels up to the point of change is M I-
The I code is output, and as the access signal for the latter half of the code, one M Simultaneous read operations are performed to solve the first problem.

Second, if a make-up code is also output at the same time as the above-mentioned MH code output, the MH code length that should be output at one time as an MH code output may become too long.

Therefore, the makeup code is output in advance before the change point appears in the n bits of the parallel signal. In other words, by looking at the n bits of the parallel signal and the n bits of the next parallel signal at the same time (this is called parallel signal look-ahead operation), changes can be made even if there is no change point in the n bits of the parallel signal. At the same time as detecting that a point exists in the looked-ahead n bits, output a run-length make-up code that is the sum of the value of the counting circuit and the value up to the change point in the look-ahead n bits. This solves the second problem. However, in order to look ahead n parallel signals, two stages of dual parallel shift circuits are provided, the above look-ahead operation is performed using the output n bits of the first stage parallel shift circuit, and the second stage parallel It is necessary to perform two series of basic operations and multiple termination codes with the output n bits of the shift circuit.

Thirdly, when the run length exceeds 2623, it is necessary to output two makeup codes, and -
If only the above method () is used, the length of the code output at one time becomes long, which is inconvenient.

Therefore, a look ahead operation is performed, and if it is determined that the run length exceeds 2560 even if there is no change point, the make-up code "2560" is output first, and the make-up code "2560" is By outputting the make-up code in advance of the output of the make-up code, the two make-up codes can be outputted twice, and the third problem in item 2 can be solved.

In this way, by converting the image information into parallel signals of n bits each and sequentially performing the above-described processing on the n-bit parallel signals, the run length counting operation and the MH code table access operation are performed (image manual clock tXn) - 2 time M I-T image compression device can be realized.

Next, the operation of one embodiment of the present invention will be described in detail based on the drawings.

However, in this embodiment, n=
Give 4. If n is set too large, the total coat length when generating multiple MH codes at once becomes long (nearly required for narizugi processing), but if n = 4, one M T (M output by code access
The I-T code length is within a maximum of 16 bits, and a time of 2t is given as the above-mentioned MI (code access time).

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining FIG. 1. First, the components of FIG. 1 will be described.

In FIG. 1, the input signal B is the main scanning signal I3 representing the main scanning time in the scanning (during the main scanning, 'H
). Signal A is an image information signal input to the hit serial. Image information signal A represents black when it is "H'" and white when it is "17". The input signal S is a clock signal for sampling image information pixel by pixel from the image information signal. The period of the clock signal S is the pixel reading period t.

], 01 is a timing generation circuit that generates waveforms necessary for the operation of this embodiment.

102 is a serial shift register circuit that converts the image information signal into 4-hit parallel signals. 1.03. 10/1
is a 4-hit para-I nor shift register circuit that receives the above-mentioned image information in 4 bits each.

Reference numeral 105 denotes a control circuit constituted by a ROM circuit that switches to different MI-I encoding operations according to the combination of white and black of the 4-hit contents of the 4-hit differential offset recorder circuit I04.

107 and 108 are counting circuits that count run lengths. Here, 1.07 is a 64-decimal counting circuit that calculates the run length of the termination code, and 108 is a make-up code counting circuit that counts the carry from the counting circuit 107.

109, 1]0. 1.11 is a ROM circuit that stores the MH code table. ROM circuit] 09 is a termination code table and a code length table of the terminator code, ROM circuit] 10 is a makeup code and a makeup code length table, and ROM circuit 1] 1 is a terminal code table and a code length table of the termination code. A termination code table for outputting to a signal line, a total code length table of a plurality of output termination codes, and a numerical value table for run length counting output to the counting circuit 107 (details will be described later).
I remember.

115 is the aforementioned bit shifter circuit that fills the MH code output from the ROM circuit without any gaps.

106, 112. ] 14 is a flip-flop circuit which will be described later, and 113 is a gate circuit.

In the circuit shown in FIG. 1 having the above configuration, the serial shift register 102 shifts the image signal bit-by-bit serially input, and the parallel shift register 103 shifts the serial shift register 102 by n bits (4 bits in this embodiment). Each time an image signal of 1 is shifted, n bits of the shifted image signal are received, and the parallel shift 1 register 104 transfers the n bit image signal received by the parallel shift register 103 to a new n bit image signal from the serial shift register 102. The image signal is received every time the image signal is shifted in parallel to the parallel shift register 1.03. Then, the pattern of n parallel signals received by the parallel shift register 104 is divided into four types, and the following different processes corresponding to the patterns are performed to convert the image signal into M in real time.
I-1 encoding is performed.

(Process 1) Output of a plurality of termination codes when image information of different colors exists in the contents of the parallel shift register 104.

(Process 2) Performed when the n bits of the parallel shift register 104 have the same color, and the first bit of the image information input among the n bits of the parallel shift register 103 is different from the color of the n bits of the parallel shift register 104. Output of makeup code and terminator 1 code.

(Process 3) The content n bits of the parallel shift register 104 are the same color, and the color of the first bit of image information input among the contents of the parallel shift register 103 is also the same color, and the n- bits other than the earliest input bit are the same color. Output of makeup code when there is image information of different colors in 1 bit.

(Processing 4) When the content n of the parallel shift register 104 and the content of the parallel shift register 103 are the same color, and the number of continuous pixels of the same color exceeds 2560, make-up code = output of "256o" , or an operation in which no MH code is output when the number of consecutive pixels of the same color does not exceed 2560.

Next, the operation of the illustrated circuit will be explained step by step.

The main scanning signal B (signal B in FIG. 2) activates the timing generation circuit 101 at "H". Timing generation circuit 10
A clock signal S (signal S in FIG. 2) is also input to the 4-hit parallel shift register 103.
(hereinafter referred to as register 103) and a shift signal E (signal E shown in FIG. 2) of 4-bit parallel shift register 104 (hereinafter referred to as register 104).

As shown in FIG. 2, the interval at which the shift signal E is generated is hereinafter referred to as T.

On the other hand, the image information signal M A input in bit serial
(Signal A in Figure 2) is serial software l-+nosistor 1
02 (hereinafter referred to as register j02), and register 1
02, C3, C2, C] and Co are shifted in this order. As shown in Fig. 2, when 4 hits of information for the first 4 pixels are input to the image information signal, the shift signal E becomes "H".
Therefore, when register +02 is filled with the first 4 bits of image information signal A, shift signal E causes register ], 0
Parallel shift to 3.

Similarly, when the next four bits are filled in the register], 02, the contents of the register 103, that is, the first four bits of the image information signal A, are shifted to the register 104 in parallel. In this way, the first four bits of image information are stored in register 104.
Then, the next four bits are shifted to register 103.

Thereafter, in the same way, the image information of the image information signal A is transferred to the register 104 and the register 104 and 03 at intervals of T, respectively.
detected.

When the first four bits of image information are shifted into register 104, the MH encoding operation described below begins.

As mentioned above, in this embodiment, the I no register 104
Different encoding operations are performed depending on the combination of 4-pit white and black of the image information that has been parallel-shifted. A control circuit 105 constituted by the ROM circuit controls switching of this encoding operation. As shown in FIG. 1, the input line (address line) of the control circuit 105
The outputs of the second register 10/I and the register 103, the output of the termination counting circuit 107, and the output signal C (signal D in FIG. 2) of the timing generation circuit 101 are input to the circuit. This input accesses data previously stored in the control circuit 105, and the output switches the operations described below. Here, the signal C is a signal having a period four times that of the clock signal S, and as shown in C of FIG. This is the signal that is applied in the second half T2.

Table 1 shows the operation depending on the combination of contents of register 104. In (1) of Table 1, aO9al, a
2. a3. bo is the signal aO9 in FIG.
al, a2. a3. It shows the contents of bo.

(2) in Table 1 is ``2'' at T1 and T2 in Figure 2.
The control circuit 105 stores the ROM 109. ROMl
10° ROM11] to be accessed. This control is performed by signals F, G, and H in ROM1.09. ROM1.1. O,R,0
This is done by controlling the chip enable terminals of M1], ] to enable only the ROM to be accessed.

(1) to (14) in Table 1 indicate points of change in the contents indicated by register 04 (if a pixel whose color differs from the previous pixel's image information in image information signal A is input, the image representing this pixel) This represents the case where there is information (called a change point). (15) to (18) show the case where there is no change point in register 04.

As shown in (2) of Table 1, the aforementioned ROM access switching can be divided into three cases. (1) If there is a change point in register 04 (corresponding to process 1 of the claims) (2) There is no change point in register 04, and bo of register 105 is the change point (corresponds to process 2 in the claims) (3) When there is no change point in register 04 and there is no change point in register 105 (1]0 in register 105 (corresponds to processes 3 and 4 in the claims) It is. The operations in the above three cases will be described in detail below.

(1) When a change point exists in register 04 In this case, the number of pixels for which the run length is not determined within the 4 bits of register 104 is detected, and the run length is determined within the 4 bits of the register 104. The code that has been determined (hereinafter referred to as a determined code) is outputted, and the number of pixels in the register 104 whose code has not been determined is added to the counting circuit 107. This operation will be described in detail below.

First, the control circuit 105 will be described. When there is a color change point among the four hits of register 04 ((1) to (1, 4) in Table 1), control circuit 105 registers the memory of ROM 109 for time T1 of time T. The ROM]09 is enabled by the enable signal F.

At the same time, the control circuit 105 sends information as to whether there is a previous pixel between the contents aO of the register 104 and the first change point counted from the first change point (shown in parentheses in Table 1) to the signal I. ROM]09. Control circuit 105 disables ROM]09 at time T2 and enables ROM], ]I by signal H. The above is the operation of the control circuit.

At time T1, ROMIII is (i) in Table 1 above.
A termination code is generated that is determined at the first change point shown in FIG. In this case, it is not necessary to output the makeup code, but this will be made clear later in the explanation.

The ROM 109, which was enabled at time T1, receives the continuous pixel count output by the termination counting circuit 107 as the signal J and the information indicated by the above-mentioned signal ■ as an address signal, and executes the number of runs that is the sum of both numbers. A terminator 1 code representing the length is stored in advance, a terminator code table is accessed, the signal is output in parallel, and the signal is output to the pitton lid circuit 115 described above. However, the color of the generated code is determined by inputting the signal aO to the address line and outputting the termination code having the same color as the color indicated by aO. At the same time, the code length of the output MH code is signaled and output to the pit shifter circuit 15. Furthermore, the signal M is used to notify the above-mentioned Hira I shifter circuit 15 via the OR circuit 113 that the code has been output.

(ROM 1.09, ROM] ], 0,
When an M I-T code is output from the ROM ] ], ], the code length of the M T-I code output is always changed to the pit shifter circuit 1. ], 5 is output, but will not be recorded hereafter) At time T2, from the first change point shown in (i) of Table 1, a
The MH code determined by 3 is output. Specifically, at time T2, ROM 109 is disabled and ROM]I+ is enabled by signal 11 instead. As shown in FIG. 1, ROMIII receives the contents of register 107I as address signals, signals ao, al,
a2. a3, the contents of register 103, and signal bO are input, and when ROM1], ] is enabled by signal H, ROMIII changes a3 from the first change point shown in (1■) in Table 1. The terminal 1 code determined during the wait is sent to the hit shifter 11 as a signal T.
Output to 5.

At the same time, a signal O indicating the sign output is outputted to the hit shifter 1.15 via the OR circuit 113.

If there is no change point in the register 104 and I)O after the first change point, there is no termination code determined in the register 04 after the first change point, so the code output K and the above signal O are not output.

At the same time (at time T2), ROM III applies the undetermined number of pixels in the register 104 (Table 1 (V)) to the counting circuit 107 as a signal P. The number of applied pixels is added to the contents of the counting circuit 107 itself at the same time as the next 4-hit parallel register is shifted, but before the addition, the counting circuit 107 is cleared (the contents are set to O). This is done in order to clear the numerical value output as the terminus I code and start counting the run length anew since the termination code up to the contents in the register 104 has been output.

This operation can be achieved as follows. That is, when the sign output signal O is output in FIG. 1, it is necessary to clear the above-mentioned counting circuit 107. Then, the flip-flop circuit 114 (hereinafter referred to as FF circuit) is set by the signal O and reset after one period of the clock signal S, and the output Q of the FF circuit 114 clears the counter circuit 07. In this way, the operation described in -1- is realized.

(2) When there is no change point in the register and BO is the change point In this case, the run length up to the contents a3 of the register 104 is determined, so the make-up code (output at time T) representing this run length during time T ) and a termination code (output at time T2).

The detailed operation will be described below.

First, the operation of the control circuit 105 in case (2) will be described. If there is no change point in the 4 bits of the register 104 and bo is the change point, the control circuit 105 returns at time T as shown in Table 1 (ii).

ROM1. ]0 is enabled, L11ROM in T2]10 is disabled and the ROM is placed instead.
Enable +09.

Further, at time T1, the control circuit 105 determines that if the value indicated by the termination counting circuit 107 is 60 or more,
In other words, if you add the number of 4-bit pixels of the same color in the register 104, the number will be 64 or more, so the number of make-up digits will be reduced to RO.
M+, make-up digits to inform 1.0''-
The output signal R is output to ROM 1 ] and O. Also, at time 'F2, the value 4 for 4 pixels in register ] 04
The signal ■ is output to ROM 1.09. The above is the operation of the control circuit 105.

Now, at time T, ROMI], O is the value of the make-up old number circuit 108, the above-mentioned make-up digit, a signal R, a signal S (not outputted in the case of (2) mentioned above, which will be described later), and a register 104. By aO times the signal, AI・
accessed from the reply line. And the summary ROMl
The value indicated by the makeup counting circuit 108 and the makeup digit from the makeup code table stored in l0.
The make-up code indicated by the number added to the output of the Niri signal (O or 1) is accessed, and the make-up code is output as a signal to the bit shifter circuit 115. At the same time, the code output signal is output to the bit shifter circuit 115 via the MOR circuit 113.

At time T2, the termination code corresponding to the run length obtained by adding the value indicated by the termination 1-old number circuit 107 from ROM 1.09 and the value 4 for the 4 pixels present in register ], 04 is output as signal I. do. To be more specific, as described above, the ROM 109 contains the output signal J of the terminus 1/counting circuit 107 and the control circuit 10 described above.
5 output signal I and a register IO4 indicating the color of the output code.
The output aO is input to the address line, and the terminal
1 to the numerical value 4 indicated by the signal I to the non-indicated value of the counting circuit 107.
bit shifter circuit corresponding to the run length plus the terminator 1 and sign indicating the same color as the signal aO]
Output to 15. At the same time, the sign output signal M is ORed]1
3 to the bit shifter circuit 115.

Here, the contents of the make-up counting circuit 108 and the terminus-1/counting circuit 107 have been converted to the M T-1 code, so the contents of the make-up counting circuit 108 and the terminus-1/counting circuit 107 have been converted to the M T-1 code, so the contents of the make-up counting circuit 108 and the terminus-1/counting circuit 107 have been converted to M T-1 codes. 108 must be cleared (content set to O). This operation is realized as follows. That is, the output signal I of the control circuit 105
If the value 4 is output from , it is necessary to clear twice. The FF circuit 106 is "2". Detects the value 4 of the signal (■) and sets it at the end of time 2.
Reset at the end of time T1 in Norshift operation. The output signal V of this FF circuit 106 causes a counting circuit 107,
By clearing 108, two consecutive operations are possible.

(3) There is no change point in register 104 and register 1
When there is no change point in bo of 05, the operation of the control circuit 115 will be explained first.

In the case of (3), control circuit 1.1 of (i) in Table 1
5 enables ROMITo at time T, time]
2. Enable ROMIII.

In this embodiment, if the run length exceeds the maximum value of the makeup code "2560", even if a color change point is detected, it is not detected (but the makeup code "2560°" is output). In order to control this operation, the control circuit 115 transmits a signal S, which will be described below, at a time T.
Output to I. That is, the signal S has no change point between the contents of the register 1071 and the contents of the register 103;
If 7 indicates 56 or more, that is, the value indicated by the termination number circuit and register 103, register] 04
R,OM 1.1 If you add 8 hits for the image information, the number will be 64 or more, which will cause an order of magnitude difference in makeup.
This is a signal to notify 0.

Here, it is necessary to actually output the make-up code 2560 not only under the conditions for outputting the ``2'' signal S, but also that the make-up counter circuit 1.08 points to the number 39 (make-up counter 40 of the circuit 108 corresponds to the makeup code 2560), but for this condition, when the signal S is output, ROM 1.1
Judge with 0 (described later).

In addition, the control circuit 105 sends the "make-up digit" signal R to the register 103 as described in case (2).
3 pins other than O 1-bl, b2. b3 has a change point, and the sum of the number of pixels between the first change point in register 10/l and the first change point in register 10/l is 64 or more, counting from the signal aO in register 10/l is 64 or more If so, it is output at time T1. The following is an explanation of the operation of the control circuit 105.

Now, at time 1゛1, FIG. 2 ROM ] ] 0 is the content of FIG. 2 register 103 1) ], , b 2 ,
If +33 is the change point, the makeup code indicated by the value of the makeup counting circuit 108 plus the value (0 or 1) of the makeup digit 1 minus signal R is stored in the makeup code table. It is accessed and output as a signal R to the bit shifter circuit 115. At the same time, a signal N indicating that the code has been output is outputted to the pit shifter circuit 115 via the OR circuit 113. However, if the value indicated by the make-up counter circuit is 0 and the value indicated by the carry signal R is also O, it means that the run length determined at the above change point is 63 or less, so in this case, the make-up code is does not output signal R or signal N indicating that it has been output.

Furthermore, when the output request signal S of the makeup code 2560 is input to the ROM], 10, and the value indicated by the signal U of the makeup counter circuit is 39, the ROMll0 accesses the makeup code table using the signal S and the signal U. and outputs a makeup code 2560.

As mentioned above, in case (3), T, make up.

Output the sign. At time T2, the MH code is not output, but the operation described below is performed. That is, since the makeup code has been output, the contents of the makeup counting circuit 108 are cleared (set to 0). Simultaneously terminate counting circuit 10
7, the value 4 corresponding to 4 bits of the register 104 is output as a signal P from the ROM 111 enabled at time T2 by the signal H and is applied. This is the next register 10
3 to register] and 04, it is added to the termination counting circuit 107. However, in the result of this addition, a carry operation from the terminus 1 counting circuit 107 to the makeup counting circuit 108 is prohibited for the following reason.

That is, as described above, this digit is already taken into account by the makeup carry signal R at time T1 and the makeup code is output from ROMI]O.

Clearing the makeup counting circuit 108 and the above digit -1
The ban on Niri can be implemented as follows.

That is, if the value of the signal P output from ROM 1-] 1 to the terminus-1 counting circuit 107 at time T2 is 4, the above-mentioned make-up counting circuit 0
This is a case where it is necessary to clear the number 8 and prohibit the above-mentioned carry. That is, when the output value of the signal P is 4, the contents of the makeup counter circuit 11 may be cleared during the next parallel shift from the register 104 to the register 103. Here, when the output value of the signal P is 4, the FF circuit 112 detects this, performs a cell I-, and resets it after the time T of the next shift. The output signal W of this FF circuit 106
By clearing the makeup counting circuit while this one word W is being output, the above-mentioned clearing and prohibition of the carry operation can be realized.

The above is an explanation of the operation in case (3). As is clear from the above, when outputting a make-up code with a run length of 64 or more, either the above (2) or (3)
) outputs a makeup code.

In other words, the change point in the next parallel shift is register 1.0.
4 and when the case (1) is reached, the output of the makeup code has already been completed, and there is no need to output the makeup code in the operation (1). This (1,
), (2), and (3) in register 104.
, it is possible to perform the MH encoding operation in real time by executing each 4-bit parallel shift of the register 103.

The above is the explanation of the part that converts the image information A into MW Kotsu.

In this way, ROM109. ROMll0. ROM11
Ml (code signal R, MI-
The 1 code signal T is input to a bit shifter circuit]15.

[Bit shifter circuit] At the same time, a signal indicating the code length is input to the bit shifter circuit 15. Also, the signal M shows no sign output.

The signal N and the multiplied signal are inputted via the OR circuit 113.

As described in the conventional example, the pit shifter circuit 115 is
The signal X indicating the output of the H code causes the MH code and MH
Receive code length. Then, by taking the number of bits indicated by the MH code length, the M -I code is extracted from the parallel signal line, and the extracted MH code is packed without any gaps and output as the parallel signal Y. be.

According to the configuration of the embodiment, the M H code table (ie, ROM], 09.ROMll0.ROM1], 1.
) is 2t, which is twice the t of the conventional example, and considering the access delay time of the ROM circuit, MH code compression operation is possible for images that are input faster. .

〔effect〕

As described above, according to the present invention, input images can be compressed at high speed without any delay in input.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image processing device to which the present invention is applied, FIG. 2 is an operation timing chart of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing an example of a conventional configuration. circuit, 102 is a serial shift register circuit, 1.03. 104 is a parallel shift register circuit, 105 is a control circuit, 107°10
8 is a counting circuit, and 109 to 111 are ROM circuits.

Claims (1)

[Claims] The input image information is divided into n-bit units and converted into n-bit parallel signals, the parallel signals are shifted in parallel, the run length is counted in n-bit units, and MH encoding processing is performed, and the n-bits to be processed next are MH compatible with parallel signals
An image processing apparatus characterized in that a code is outputted in advance of the above processing, and a plurality of MH codes corresponding to a plurality of change points in an n-bit parallel signal to be processed are simultaneously outputted.