JPS63237154A - Memory access system - Google Patents

Abstract

PURPOSE:To realize an access system with a little overhead by switching a memory to the bus side of the second CPU side, only when an access from the second CPU arises. CONSTITUTION:The bus A and the bus B are connected to a first CPU and a second CPU respectively, and these buses are connected selectively to the memory M1 through a selector 13. The selector 13 is connected to the bus A while the access from the bus B does not exist. When the access from the bus B is generated, a request is sent to a bus switching circuit 12 through an access request circuit 11, and the bus switching circuit 12 drives the selector 13 and connects the memory M1 to the bus B side. Since a procedure to switch the selector 13 at the time of the access from the bus A, is not necessary, the overhead comes less.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory access method for a multi-CPU (Central Processing Unit) system.

(Prior art) In a conventional multi-CPU system, a bus arbitration circuit (
The memory was accessed by outputting signals to the bus through a circuit that controlled the right to use the bus. The fourth figure shows the multi-CPU system, and 11+12 in the figure shows the C
PU board, CPU1. CPU2 is a central processing unit, 21
．． 22 is a bus arbitration circuit, 3 is a memory board, 4 is a memory, and 5 is a bus. Therefore, when an access from the CPU to the memory 4 occurs, the bus arbitration circuit always operates, which causes overhead (waste time) due to the bus arbitration circuit at the time of access. This has caused a reduction in the processing power of the CPU.

(A slow point for the invention to solve) As described above, in the past, access to memory was performed through the bus arbitration circuit, which reduced the processing power of the CPU.

Therefore, an object of the present invention is to provide a multi-PU memory access method that does not reduce the processing performance of the CPU by obtaining a system bus configuration that does not reduce the access speed of the CPU.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a first CPU that directly outputs a signal from a first CPU.
a bus, a bus switching means for preferentially accepting accesses from this bus, a memory provided on the output side of this means, and a signal from a second CPU to switch the bus switching means to the second bus side. The present invention is characterized by comprising a means for switching.

That is, in the present invention, the first bus can be used when the first CPU accesses the memory, and the switching thread path is normally connected to the first bus side, so that memory access can be performed at high speed. Therefore, it is possible to improve the processing power of the CPU.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a configuration diagram of the same embodiment, and is 1□.

12 is a CPU board, CPU1, CPU2 are central processing units, 2nd board, 22 is a bus arbitration circuit, 31°32 is a memory board, M□, M2 are memories, A is a bus that directly outputs the signals of CPU□ (CPU1 Dedicated bus), B is a bus compatible with the multi-CPU system, and 9 is a circuit for switching bus signals between buses A and B.

FIG. 2 shows a specific example of the switching circuit 9, and 10 is a bus A.
il is a circuit that accepts access from bus B and issues a request to memory; 12 is a bus switching circuit that mediates requests from circuits 10 and 11 and performs bus switching; A circuit 13 is a selector that switches an access signal to the memory M1.

FIG. 3 is a flowchart showing the operation of the above configuration. Note that this flowchart is viewed from the CPUI, and is
This is not what I saw from PU2. First, when the CPU accesses the memory M1 (step S1),
The signal from CPU1 is output to bus A (step S
2). The signal output to the bus A is passed through the switching circuit 9 (step S3), and the memory M1 is accessed (step S6). That is, when there is no access from bus B (thread path S4), the switching circuit 12 has the logic to connect the bus A signal to memory M, and the selector 13 connects the bus A signal to memory M1. are doing. If an access from bus A occurs at this point, an access signal is transmitted to memory M1 and the memory is accessed without performing a bus switching operation.

On the other hand, if access is occurring from the CPU 2 through the bus B (Itoro S5), a request is issued from the circuit 11,
The bus switching circuit 12 issues a switching signal to the bus B, the selector 13 operates, and the bus B switches to the memory M1.
is accessed (step S7). When this access is completed, the selector 13 becomes the logic for connecting the signal on the bus A to the memory M1 (step S8).

In the above system, when the CPU accesses the memory M1, the bus Δ can be used and the thread path of the selector 13 is normally connected to the bus A, so it is possible to access the memory at high speed. , CI) U,
It is possible to improve the processing power of the computer.

[Effects of the Invention] As described above, according to the present invention, by obtaining a configuration that does not reduce the access speed of the CPU, it is possible to provide a multi-CPU memory access method that does not reduce the processing performance of the CPU.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing a part of the same structure in detail, Fig. 3 is a flowchart showing the operation of the same structure, and Fig. 4 is a conventional block diagram. Multi 〇PU
FIG. 1 is a block diagram showing a memory access method of FIG. CPU1. CPU2...Central processing unit, Ml. M2...Memory, A, B...Bus%11.12...
・CPU board, 21122...Bus arbitration circuit, 9・
...Switching circuit, 10.11... Access request circuit, 12... Bus switching circuit, 13... Selector. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4

Claims (1)

[Claims] a first bus that directly outputs a signal from the first CPU;
a bus switching means for receiving access from this bus with priority; a memory provided on the output side of this means;
A signal from the second CPU causes the bus switching means to switch to the second
A memory access method characterized by comprising means for switching to the bus side.