JPS632394A - Manufacture of semiconductor light-emitting device - Google Patents

Manufacture of semiconductor light-emitting device

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Publication number
JPS632394A
JPS632394A JP14583386A JP14583386A JPS632394A JP S632394 A JPS632394 A JP S632394A JP 14583386 A JP14583386 A JP 14583386A JP 14583386 A JP14583386 A JP 14583386A JP S632394 A JPS632394 A JP S632394A
Authority
JP
Japan
Prior art keywords
layer
diffusion
conductivity type
end surfaces
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14583386A
Other languages
Japanese (ja)
Inventor
Shuichi Miura
秀一 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14583386A priority Critical patent/JPS632394A/en
Publication of JPS632394A publication Critical patent/JPS632394A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To control diffusion depth in the lateral direction with high accuracy by diffusing the lateral direction from the end surface of a semiconductor layer as the direction of diffusion in the control of the width of an active layer being controlled by lateral diffusion vertical in the direction of diffusion in a current injection type semiconductor laser. CONSTITUTION:Active layers are laminated alternately onto an Si-GaAs substrate 11, and a photo-resist 10 is formed as an etching mask for shaping end surfaces by using normal lithography. Both end surfaces approximately vertical to each layer are shaped through reactive ion etching. Both end surfaces are coated through sputtering, and an SiO2 layer is applied onto the whole surface of the substrate as an introduction-resistant layer for an impurity. Ar ion beams are projected from the oblique lateral direction so as to be made approximately vertical to the end surfaces to etch an SiO2 layer 4, and only one end surface is exposed. Si is diffused from the end surface to shape an n-type region 5, and the SiO2 layer 4 is removed. Likewise, Zn is diffused from the end surface, employing an SiO2 layer 6 exposed to the other surface as a mask and a p-type region 7 is formed on the other side, and the SiO2 layer 6 is gotten rid of.

Description

【発明の詳細な説明】 〔概要〕 横方向(基板に平行な方向)注入レーザを形成する際の
拡散前面の形状と深さの制御性を向上するため、端面の
みを露出してその他を耐導入層でマスクして、端面より
不純物を導入する方法を提起する。
[Detailed Description of the Invention] [Summary] In order to improve the controllability of the shape and depth of the diffusion front when forming a lateral (parallel to the substrate) injection laser, only the end face is exposed and the rest is exposed. A method is proposed in which impurities are introduced from the end face using a mask with an introduction layer.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体発光装置の製造方法、とくに横方向注入
レーザの形成精度を向上した製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor light emitting device, and more particularly to a method of manufacturing a semiconductor light emitting device with improved precision in forming a lateral injection laser.

電流注入型半導体レーザにおいて、光と電流の狭窄を行
いながら電流を横方向から注入できると、p側とn側の
画電極を基板表面に形成することができるため、製造プ
ロセスが容易になり、光電子集積回路(OEIC,Qp
toelectronic IntegratedCi
rcuit)への集積化が可能となる。
In a current injection semiconductor laser, if current can be injected from the side while confining light and current, the p-side and n-side picture electrodes can be formed on the substrate surface, which simplifies the manufacturing process. Optoelectronic integrated circuit (OEIC, Qp
toelectronic IntegratedCi
rcuit).

(従来の技術〕 横方向注入レーザとしては、従来、TJS(Trans
−verse Junction 5tripe)レー
ザがあったが、層構造が電子素子と互換性がないため、
0EICには有効とはいえなかった。
(Prior art) As a lateral injection laser, TJS (Trans
-verse Junction 5tripe) laser, but its layer structure is not compatible with electronic devices, so
It could not be said to be effective for 0EIC.

第2図はTJSレーザの一例を示す断面図である。FIG. 2 is a sectional view showing an example of a TJS laser.

図において、半絶縁性(SI)−GaAs基板(Sub
、)21上にn−AlGaAs層22、活性層となるロ
ーGaAs層23、n−AlGaAs層224を順次成
長し、片側に亜鉛(Zn)を拡散してp型頭域25を形
成する。
In the figure, a semi-insulating (SI)-GaAs substrate (Sub
, ) 21, an n-AlGaAs layer 22, a low GaAs layer 23 serving as an active layer, and an n-AlGaAs layer 224 are grown in sequence, and zinc (Zn) is diffused on one side to form a p-type head region 25.

図中、点線で示される拡散前面とp型頭域25間のn−
GaAs23は真性半導体となり活性層が形成される。
In the figure, n- between the diffusion front indicated by the dotted line and the p-type head region 25.
GaAs 23 becomes an intrinsic semiconductor and forms an active layer.

活性層の長さ方向は紙面に垂直な方向となる。The length direction of the active layer is perpendicular to the plane of the paper.

p型頭域25上にはp側電極として金/亜鉛/金(Au
/Zn/Au)層26を、表面のn−AlGaAs24
の上にn側電極として金/金ゲルマニウム(Au/Au
Ge)層27を形成する。
On the p-type head region 25, gold/zinc/gold (Au
/Zn/Au) layer 26, and the n-AlGaAs layer 24 on the surface
Gold/gold germanium (Au/Au
Ge) layer 27 is formed.

以上の層構造においては、表面のn−AlGaAs24
上には電界効果トランジスタ(FET)を最適化して集
積化することはできない。
In the above layer structure, n-AlGaAs24 on the surface
Field effect transistors (FETs) cannot be optimized and integrated thereon.

そこでつぎに、電子素子と互換性を有する層構造を採用
した横方向注入レーザを説明する。
Therefore, next, a lateral injection laser employing a layer structure compatible with electronic devices will be described.

第3図は従来例による方法を工程順に説明する横方向注
入レーザの断面図である。
FIG. 3 is a cross-sectional view of a lateral injection laser explaining a conventional method step by step.

第3図(1)において、5I−GaAs基板11上に高
抵抗(HR) −Al o、 5Gao、 l、As層
1、活性層として交互に積層したAlGaAs/GaA
s層よりなるMqw (多層量子井戸)構造2、HR−
A16. 、Ga、、 、As層3を順次成長する。
In FIG. 3 (1), high resistance (HR) -Al o, 5 Gao, l, As layers 1 and AlGaAs/GaA layers alternately stacked as active layers are formed on a 5I-GaAs substrate 11.
Mqw (multilayer quantum well) structure 2 consisting of s layer, HR-
A16. , Ga, , As layers 3 are sequentially grown.

不純物の耐導入層としてバターニングした二酸化珪素(
Si(h)層4′をマスクにして、基板表面より珪素(
St)を拡散して片側にn型領域5′を形成し、Si0
1層4′を除去する。
Buttered silicon dioxide (
Using the Si(h) layer 4' as a mask, silicon (
St) is diffused to form an n-type region 5' on one side, and Si0
1 layer 4' is removed.

第f 図(2)において、パターニングした5iOz層
6′をマスクにして、基板表面よりZnを拡散して他側
にp壁領域7′を形成し、5iQz層6′を除去する。
In FIG. f (2), using the patterned 5iOz layer 6' as a mask, Zn is diffused from the substrate surface to form a p-wall region 7' on the other side, and the 5iQz layer 6' is removed.

n型領域5′とp壁領域7′は拡散処理中、拡散方向に
垂直な横方向にも拡散は進行し、両頭域に挟まれたMQ
W構造30幅、すなわち活性層の幅の制御が困難となる
During the diffusion process in the n-type region 5' and the p-wall region 7', diffusion also progresses in the lateral direction perpendicular to the diffusion direction, and the MQ sandwiched between the double-headed regions
It becomes difficult to control the width of the W structure 30, that is, the width of the active layer.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例によると、活性層の幅の制御は拡散方向に垂直な
横方向拡散の精度により決まるため極めて精度が悪い。
According to the conventional example, control of the width of the active layer is determined by the accuracy of lateral diffusion perpendicular to the diffusion direction, and therefore has extremely low accuracy.

〔問題点を解決するための手段〕[Means for solving problems]

第1図(1)〜(7)は本発明の方法を工程順に説明す
る横方向注入レーザの断面図である。
FIGS. 1(1) to 1(7) are cross-sectional views of a lateral injection laser explaining the method of the present invention step by step.

上記問題点の解決は、一導電型の第1の半導体層1と活
性層となる第2の半導体層2と一導電型の第3の半導体
層3を順次積層して形成し、前記半導体各層にほぼ垂直
な一方の端面を露出してそれ以外を耐導入層4で覆って
一導電型の不純物を前記半導体各層に導入して一導電型
領域5を形成し、 該耐導入層4を除去して、前記一方の端面に平行な他方
の端面を露出してそれ以外を耐導入層6で覆って他導電
型の不純物を前記半導体各層に導入し、かつ該一導電型
領域5に接触しないように他導電型領域7を形成する工
程を含む半導体発光装置の製造方法により達成される。
The above problem can be solved by sequentially stacking a first semiconductor layer 1 of one conductivity type, a second semiconductor layer 2 serving as an active layer, and a third semiconductor layer 3 of one conductivity type, and One end face substantially perpendicular to is exposed, the other part is covered with an introduction-resistant layer 4, impurities of one conductivity type are introduced into each of the semiconductor layers to form a one-conductivity type region 5, and the introduction-resistant layer 4 is removed. Then, the other end face parallel to the one end face is exposed and the other end face is covered with an introduction-resistant layer 6 to introduce impurities of other conductivity type into each of the semiconductor layers, and do not contact the one conductivity type region 5. This is achieved by a method of manufacturing a semiconductor light emitting device including a step of forming a region 7 of a different conductivity type.

〔作用〕[Effect]

本発明は、従来方法が拡散方向に垂直な横方向拡散によ
り制御していた活性層の幅(すなわち拡散により形成さ
れるpn接合位W)の制御を、半導体層の端面より横方
向を拡散方向として拡散することにより、高精度に横方
向の拡散深さを制御できることを利用したものである。
In the present invention, the width of the active layer (that is, the pn junction W formed by diffusion), which was controlled in the conventional method by lateral diffusion perpendicular to the diffusion direction, can be controlled in the lateral direction from the end face of the semiconductor layer. This takes advantage of the fact that the lateral diffusion depth can be controlled with high precision by diffusing as

〔実施例〕〔Example〕

本発明の実施例を第1図を用いて説明する。 An embodiment of the present invention will be described with reference to FIG.

第1図(1)において、5I−GaAs基板11上にH
R−A16. aGao、 6AS層(第1の半導体層
)1、活性層として交互に積層したAlGaAs/Ga
As NよりなるMQ−構造(第2の半導体層)2、H
R−Ala、 aGao、 hAs層(第3の半導体層
)3を順次成長する。
In FIG. 1(1), H
R-A16. aGao, 6AS layer (first semiconductor layer) 1, AlGaAs/Ga stacked alternately as active layer
MQ-structure (second semiconductor layer) made of AsN 2, H
R-Ala, aGao, and hAs layers (third semiconductor layer) 3 are grown in sequence.

つぎに、通常のりソグラフィを用いて端面形成のための
エツチングマスクとしてフォトレジスト10を形成する
Next, a photoresist 10 is formed as an etching mask for forming the end face using normal lithography.

フォトレジストはマイクロポジット1300−37を用
いた。
Microposit 1300-37 was used as the photoresist.

第1図(2)において、エツチングガスとして三塩化硼
素(BCl2)十塩素(C12) を用いたりアクティ
ブイオンエツチング (RIE)により前記半導体層を
エツチングして各層にほぼ垂直な両端面を形成する。
In FIG. 1(2), the semiconductor layer is etched using boron trichloride (BCl2) decachloride (C12) as an etching gas or by active ion etching (RIE) to form both end faces substantially perpendicular to each layer.

第1図(3)において、スパッタリングにより両端面を
覆って基板全面に不純物の耐導入層として厚さ8000
人の5iCh層4を被着する。
In Fig. 1 (3), a layer with a thickness of 8,000 mm is formed by sputtering to cover both end faces and form an impurity introduction-resistant layer on the entire surface of the substrate.
Deposit the human 5iCh layer 4.

第1図(4)において、アルゴン(Ar)イオンビーム
エツチング法を用いて、Arイオンビームを端面にほぼ
垂直になるように斜め横より照射してSiO□層4をエ
ツチングし、片端面のみを露出する。
In FIG. 1 (4), using the argon (Ar) ion beam etching method, the SiO□ layer 4 is etched by irradiating the Ar ion beam from the side obliquely so that it is almost perpendicular to the end face, and only one end face is etched. be exposed.

第1図(5)において、片端面の露出された5ift層
4をマスクにして、端面よりSiを拡散して片側にn型
領域5を形成し、SiO□層4を除去する。
In FIG. 1(5), using the exposed 5ift layer 4 on one end face as a mask, Si is diffused from the end face to form an n-type region 5 on one side, and the SiO□ layer 4 is removed.

Siの拡散は、ソースにStの蒸着膜を用いて800℃
で固相拡散を行い2.濃度10”cm−”程度にドープ
する。
Diffusion of Si was carried out at 800°C using a deposited St film as a source.
Perform solid phase diffusion with 2. Dope to a concentration of about 10"cm-".

第1図(6)において、同様に他端面の露出されたSi
02層6をマスクにして、端面よりZnを拡散して他側
にp型頭域7を形成し、その後Si02層6を除去する
In FIG. 1 (6), similarly, the exposed Si on the other end surface
Using the Si02 layer 6 as a mask, Zn is diffused from the end face to form a p-type head region 7 on the other side, and then the Si02 layer 6 is removed.

Znの拡散は、ソースにZnAs、を用いて封管中で6
00℃で加熱して行い、濃度10”cm−’程度にドー
プする。
Zn was diffused in a sealed tube using ZnAs as a source.
This is done by heating at 00° C. and doping to a concentration of about 10 cm −’.

この場合も、n型領域5とp型頭域7に挟まれたMQ−
構造3の幅が活性層の幅となり、これを1μmに形成す
る。
In this case as well, the MQ-
The width of the structure 3 becomes the width of the active layer, which is formed to be 1 μm.

n型領域5上にn側電極として厚さ2700/300人
の 1デ Au/AuGe層lを形成する。
An Au/AuGe layer 1 with a thickness of 2700/300 mm is formed as an n-side electrode on the n-type region 5.

以上により、本発明による工程を終わる。This completes the process according to the present invention.

実施例においては、活性層にMQWを用いたが、これの
代わりに単層構造のものを用い手もよい。
In the embodiment, MQW was used for the active layer, but a single layer structure may also be used instead.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によれば、横方向注入
レーザにおいて、活性層の幅の制御を精度よく行える。
As described above in detail, according to the present invention, in a lateral injection laser, the width of the active layer can be controlled with high precision.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(1)〜(7)は本発明の方法を工程順に説明す
る横方向注入レーザの断面図、 第2図はTJSレーザの一例を示す断面図、第3図は従
来例による方法を工程順に説明する横方向注入レーザの
断面図である。 図において、 1はHR−Ale、 aGao、 6A3層・2は活性
層でMQ−構造、 3はIIR−Ale、 aGao、 bAs層、4は不
純物の耐導入層でSiO□層、 5はn型領域、 6は不純物の耐導入層で5iOz層、 7はp型頭域、 8はp側電極でAu/Zn/Au層、 9はn側電極でAu/AuGe層、 10はレジスト、 11は5I−GaAs基板 草1図 革3図
Figures 1 (1) to (7) are cross-sectional views of a lateral injection laser explaining the method of the present invention step by step; Figure 2 is a cross-sectional view of an example of a TJS laser; and Figure 3 is a cross-sectional view of a conventional method. FIG. 3 is a cross-sectional view of a lateral injection laser explained step by step. In the figure, 1 is HR-Ale, aGao, 6A3 layer, 2 is active layer with MQ-structure, 3 is IIR-Ale, aGao, bAs layer, 4 is impurity introduction resistance layer, SiO□ layer, 5 is n-type 6 is an impurity introduction resistance layer and is a 5iOz layer, 7 is a p-type head region, 8 is a p-side electrode and is an Au/Zn/Au layer, 9 is an n-side electrode and is an Au/AuGe layer, 10 is a resist, and 11 is a resist. 5I-GaAs substrate grass 1 figure leather 3 figures

Claims (1)

【特許請求の範囲】 一導電型の第1の半導体層(1)と活性層となる第2の
半導体層(2)と一導電型の第3の半導体層(3)を順
次積層して形成し、 前記半導体各層にほぼ垂直な一方の端面を露出してそれ
以外を耐導入層(4)で覆って一導電型の不純物を前記
半導体各層に導入して一導電型領域(5)を形成し、 該耐導入層(4)を除去して、前記一方の端面に平行な
他方の端面を露出してそれ以外を耐導入層(6)で覆っ
て他導電型の不純物を前記半導体各層に導入し、かつ該
一導電型領域(5)に接触しないように他導電型領域(
7)を形成する 工程を含むことを特徴とする半導体発光装置の製造方法
[Claims] Formed by sequentially stacking a first semiconductor layer (1) of one conductivity type, a second semiconductor layer (2) serving as an active layer, and a third semiconductor layer (3) of one conductivity type. Then, one conductivity type region (5) is formed by exposing one end face substantially perpendicular to each of the semiconductor layers and covering the rest with an introduction-resistant layer (4), and introducing impurities of one conductivity type into each of the semiconductor layers. Then, the introduction-resistant layer (4) is removed to expose the other end face parallel to the one end face, and the rest is covered with the introduction-resistant layer (6) to introduce impurities of other conductivity type into each of the semiconductor layers. and the other conductivity type region (5) so as not to contact the one conductivity type region (5).
7) A method for manufacturing a semiconductor light emitting device, comprising the step of forming.
JP14583386A 1986-06-20 1986-06-20 Manufacture of semiconductor light-emitting device Pending JPS632394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14583386A JPS632394A (en) 1986-06-20 1986-06-20 Manufacture of semiconductor light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14583386A JPS632394A (en) 1986-06-20 1986-06-20 Manufacture of semiconductor light-emitting device

Publications (1)

Publication Number Publication Date
JPS632394A true JPS632394A (en) 1988-01-07

Family

ID=15394166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14583386A Pending JPS632394A (en) 1986-06-20 1986-06-20 Manufacture of semiconductor light-emitting device

Country Status (1)

Country Link
JP (1) JPS632394A (en)

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