JPS63244873A - Semiconductor input protective device - Google Patents

Abstract

PURPOSE:To provide input protection without the change of input characteristics caused by an input protector by a method wherein a negative potential or a potential higher than a VSS potential is applied to the gate electrode of a protective transistor. CONSTITUTION:The output of an oscillation circuit 1 is connected to the input terminal of a charge pump capacitor 2 through an amplifier 9. The output terminal 3 of the capacitor 2 is connected to two terminals of a 1st transistor 4 and one terminal of a 2nd transistor 5. The other one terminal of the transistor 4 is connected to a reference potential 6 and the other two terminals of the transistor 5 are connected to the output terminal 7 of a substrate bias generating circuit. When the potential of the output terminal 3 becomes higher than the reference potential 6, the transistor 4 is turned ON and a current is applied to the reference potential 6 to make the potential of the output terminal 3 a reference potential.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor input protection device, and particularly to a semiconductor device in which the substrate bias potential is different from the ground potential or the supply potential. It is used for input protection.

(Conventional technology) A conventional semiconductor input protection device is shown in FIG.

In other words, the transistors T1 and T which serve as input protection devices
2 is connected to the ground 6 (Vss), and the potential of the input terminal 11 is within the normal operating range (Vc a -Vs
s range), transistors T1 and T2 are in a cut-off state and essentially do not affect the internal circuit 12.

If the potential of the input terminal 11 is much higher than the power supply VCC, V S
Mainly transistor T1 or T is connected to S or VCC.
2, thereby eliminating the burden of high energy on the internal circuit 12.

When the potential of the input terminal 11 is much lower than the ground Vss, the MOS transistor T2 or T1 is mainly turned on and current flows to protect the internal circuit 12.

(Problem to be Solved by the Invention) Originally, in an input protection device, under conditions within the normal specification range, transistors T1 and T2 are completely cut off, and the input terminal 11 and internal It is necessary not to affect the circuit 12, but when the temperature is high or the channel length of the protection transistor becomes narrow due to manufacturing variations, it is necessary to lower the threshold voltage yth of the MOS transistor. When the
Even if the above-mentioned temperature, channel length, threshold voltage, etc. are within the permissible range, there is a problem in that the leakage current of the MOS transistor of this input protection device increases.

Since the input leakage (leakage current at the input terminal 11) base is specified in the LSI, if there is leakage from the transistors Tl and T2, it becomes even more difficult to satisfy the above specifications.

Furthermore, if the channel lengths of the protection transistors T1 and T2 are set large in advance in order to satisfy the specifications, the protection transistors will not be able to fulfill their original purpose of protection.

An object of the present invention is to perform input protection without changing input characteristics using an input protection device.

[Structure of the invention] (Means and effects for solving the problems) The present invention has the following features:
and a second potential, in which one or more transistors are connected between an input terminal and the first potential or the second potential, and an input gate terminal of the transistor is connected to the first potential or the second potential. a third potential is connected, the third potential being outside the range between the first potential and the second potential, causing the transistor to be cut off during normal operation; The semiconductor input protection device is characterized in that a current flows through the transistor when a voltage outside the range is applied to the semiconductor input protection device. That is, for example, when the input protection transistor is an N-channel transistor, a potential Vss lower than the ground potential is supplied to the input gates of the transistors T1 and T2, and during normal operation, T1. This is a circuit in which T2 is completely cut off so that it does not affect the LSI characteristics such as input leakage current. Note that a normal NMO8LSI has a built-in negative potential generation circuit to increase the operation speed, and there is no need to prepare the negative potential generation circuit for the protection circuit.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of the same embodiment, but since this is an example in which it corresponds to the one described above, the same reference numerals are used for corresponding parts. Here, in the case of an N-channel transistor, the substrate bias generation circuit 21 provides a potential lower than the reference potential (Vs s ) as a substrate bias, and many product outputs are sent to the charge pump via the amplifier 9.
Connect to the input terminal of capacitor 2. The output terminal 3 of the charge pump capacitor 2 is connected to a first transistor 4.
and one terminal of the second transistor 5, the other one terminal of the first transistor 4 is connected to the reference potential 6, and the other two terminals of the second transistor 5 are connected to the substrate bias generating circuit. The output, ie, the continuous pulses generated by the generator circuit 1, is caused to transition at the output terminal 3 by the capacitor 2. When the potential of the output terminal 3 becomes higher than the reference potential 6, the first transistor 4
turns on, current flows through the reference potential 6, and the potential of the output terminal 3 is set to the reference potential. Conversely, when the potential of the output terminal 3 is lower than the reference potential 6, the first
The transistor 4 is turned off and the potential of the output terminal 3 is maintained.

Next, when the potential of the output terminal 7 of the substrate bias generation circuit is higher than the output terminal 3, the second transistor 5 is turned on, and the potential of the substrate bias output terminal 7 is changed to
The potential of the output terminal 3 is set.

Conversely, the potential of the substrate bias output terminal 7 is the same as that of the output terminal 3.
If the voltage is lower than , the second transistor 5 is turned off and the potential of the substrate bias output terminal 7 is maintained.

As described above, the potential of the substrate bias circuit output terminal 7 is held at the negative potential VB.

Therefore, the N-channel transistors T1 and T2
By connecting the input gate of transistors T1 and T2 to VSE, which has a potential lower than VSS, the gate-source potential of transistors T1 and T2 becomes a negative potential in the normal operating potential range.
2 into a complete cut-off state with no leakage current.

The potential of input terminal 11 is the power supply ■. . Vss or Vss, depending on the breakdown characteristics and transistor action of transistor T1 or T2.
. A current is passed through the transistor through the internal circuit 12.
Absorbs high energy without giving it to.

Further, when the potential of the input terminal 11 is much lower than Vss, the MOS transistor T1. T2 operates to pass current and protect the internal circuit 12.

Substrate bias generation circuit (minus potential VBB generation) 21
is provided in a normal NMO8LSI, and by making the substrate potential negative, the diffusion capacitance is lowered and the operation speed is improved.

Therefore, no new preparations are made for the supply of negative potential to this input protection device.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, input protection transistors T1. Although T2 is an N-channel, in the case of a substrate bias generation circuit using a P-channel, the transistor T1
．． T2 can also be a P-channel MOS transistor. Further, in the present invention, the transistor T1. T2
It can also be applied when using either one of them.

〔Effect of the invention〕

The conventional protection circuit method fulfills its role as a protection circuit, but it can be used when temperature conditions become severe, when the channel width of the protection transistor becomes narrow, or when the threshold voltage of the MoS transistor is low. , the operating conditions are within the specification range, whereas the present invention has a negative potential (N-channel MO) applied to the gate electrode of the protection transistor.
This is an input protection device that has the advantage of not affecting the initial characteristics at all during normal operation by supplying a potential higher than the VSS potential (for P-channel MOS transistors) or VSS potential (for P-channel MOS transistors). .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional device. 11...Input terminal, 12...Internal circuit, 21...
Negative potential generation circuit, T1. T2...Input protection transistor. Applicant's agent Patent attorney Takeshi Suzue Foolish plan Figure 1 Figure 2

Claims (1)

[Claims] In a semiconductor device that operates between a first potential and a second potential, one or more transistors are connected between an input terminal and the first potential or the second potential, and an input gate of the transistor is connected to the semiconductor device. A third potential is connected to the end, the third potential is outside the range between the first potential and the second potential, and cuts the transistor during normal operation.
A semiconductor input protection device characterized in that the transistor is turned off and a current flows through the transistor when a voltage outside the range is applied to the input terminal.