JPS6324896Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic scanning ultrasonic tomography apparatus, and particularly to a gain control device for a high frequency amplifier used therein.

In ultrasonic tomography devices, the dynamic range of reflected echoes from living organisms is wide, at over 100 dB, so when strong reflected echoes are input, the high-frequency amplifier becomes saturated, the bias point moves, etc., and nearby weak echoes are masked. There are drawbacks to doing so.

Therefore, conventionally, time gain control (Time gain control), which controls the gain over time in synchronization with the transmitted pulse, has been used.
Gain Control (abbreviated as TGC) is being implemented.
That is, as shown in FIG. 1, in the case of electronic scanning linear scan, the gain control voltage is as shown in curve 1.
Becomes TGC voltage. Here, the gain is reduced near the presence of strong echoes (the portion indicated by P in FIG. 1). In FIG. 1, S indicates a body surface position, D indicates a deep position, and SL indicates a scanning line.

However, if minute echoes (shaded areas in FIG. 1) exist in the arrangement direction (x direction) of the array elements, there is a drawback that they are masked by strong echoes as shown in FIG.

Therefore, in the present invention, scanning line gain control (scanning line gain control in the scanning line direction (in the case of linear scan, the x direction in Figure 1, in the case of sector scan, in the angular direction) is performed.
The aim is to add a new function (Line Gain Control).

That is, in Fig. 1, if the scanning line width of linear scan is L, a scanning line gain control (SLGC) curve is obtained for the distance x in the range of x = 0 to L, and the gain of the amplifier at each point of the tomographic image is calculated. The control signal is like curve 2
It is the sum or product of TGC and SLGC.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, in which 1 is a high frequency amplifier, 2 is a time gain control voltage generator, 3 is a scanning line gain control voltage generator,
4 is an arithmetic unit which obtains a sum signal or a product signal and controls the gain of the high frequency amplifier 1; 5 is an ultrasonic probe, and 6 is a high frequency amplifier output terminal.

Further, referring to FIG. 3, the present invention will be explained in detail with a concrete block diagram.

In FIG. 3, 7 generates the first clock signal _cl1 . 8 is a frequency divider (1/6 in the case of Fig. 3) for generating the transmission pulse, and 9 is the second clock signal cl ₂
A frequency divider (1/3 in the case of Figure 3) to generate
10 is a frequency divider (optional in the case of FIG. 3) for generating a frame control signal, 11-1 and 11
-2 is a control voltage generation circuit shown in FIG. 4, which will be described later;
In is a TTL signal input terminal, _cl1 is a clock pulse input terminal, and Out is a control voltage output terminal. That is, the control voltage generation circuit 11-1 is supplied with an input signal synchronized with the transmission signal repetition pulse and a clock signal with a shorter cycle, and the control voltage generation circuit 11-2 is supplied with the frame repetition pulse of the display. A clock signal is provided which is synchronized to the input signal and which is generated on each occurrence of a plurality of scan lines (in this case three scan lines) of the display. 12 is an arithmetic unit that executes a sum or product operation. 13 is an output terminal, which serves as a control voltage for the high frequency amplifier 1 shown in FIG.

Control voltage generation circuits 11-1 and 11 in FIG.
-2 will be explained in more detail using FIG. 4.

In FIG. 4, 20 is a shift register, 21
is an operational amplifier, 22 is a low-pass filter, TR
is a transistor, +V is a power supply, and R ₁ , R ₂ , and R ₃ are resistors. In of the shift register 20 is a TTL signal input terminal, and _cl1 is a clock signal input terminal. Out
is the control voltage output terminal. The operation of the control voltage generating circuit 11-1 is described in Japanese Patent Application No. 51-23541.
52-107186). That is, inside the shift register 20, the "1" signal input in synchronization with the transmission signal is sequentially shifted in accordance with the clock input. (All bits are "0" except for the "1" bit) Therefore, the voltages corresponding to the output voltages of the multiple resistor voltage dividers shown by _R1 are output while switching sequentially, and the curve is controlled in synchronization with the transmission pulse. Voltage is generated. This curve becomes the time gain control (TGC) curve in the depth direction. The settings for this curve are
This is done by adjusting each resistor voltage divider while observing the display screen. That is, when there is only one control voltage generating circuit as in the conventional case, the gain is set to be low at the depth where a strong echo exists, and a TGC curve like 1 in FIG. 1 is obtained. On the other hand, control voltage generation circuit 11-2
has exactly the same circuit configuration, and a “1” level signal is input to the shift register in synchronization with the frame repetition pulse, and by shifting within the shift register, it corresponds to the output voltage of multiple resistor voltage dividers. The output voltages are sequentially switched, and a scanning line gain control (SLGC) curve is obtained. The sum or product of the voltages shown by the two curves is calculated by the calculator 12, and the display gain is controlled thereby. For example, if the control voltage generation circuit 11-2 is set to a curve like SLGC in FIG. 1, and the control voltage generation circuit 11-1 is set to a curve like 2 of TGC in FIG. While reducing the display output of the strong echo at the position of P, it is also possible to display minute echoes in the shaded areas in other scanning lines other than the scanning line near P. That is, since the display gain limit for the position of a strong echo can be set in any one or both of the scanning line direction and the direction perpendicular to the scanning line, weak echoes at a desired position can be observed.

The above explanation has been about linear scan, but it is clear that sector scan is also effective.

As described above, according to the present invention, by using the sum or product signal of the time gain control (TGC) signal and the scanning line gain control (SLGC) signal as the gain control voltage of the high frequency amplifier, the gain of the ultrasonic tomographic image can be increased by 2. This makes it possible to perform dimensional control, which greatly contributes to improving the performance of ultrasonic tomography devices.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the present invention, FIG. 2 is a block diagram showing the configuration of the present invention, FIG. 3 is a block diagram showing the configuration of the present invention, and FIG. 4 is a diagram showing an example of a control voltage generation circuit. be.

Claims (1)

[Scope of utility model registration request] In an electronic scanning ultrasonic tomography apparatus, a first means for generating a gain control signal in synchronization with the repeated pulses of the transmission signal, and a first means for controlling the gain in a direction perpendicular to the scanning line in synchronization with the frame repetition pulses of the display device. An ultrasonic tomography apparatus comprising a second means for generating a control signal, the sum or product signal of the respective output signals of the first means and the second means being used as a gain control signal of a receiving amplifier. .