JPS63257785A - Scan frequency conversion system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Outline: Input image signals are alternately written into two frame memories that store one frame of input image signals by switching and controlling input switch means. When the input image signal written in the frame memory is taken out as an output image signal by switching the output switch means DT, the number of times the input switch means is switched during one frame period of the output signal is counted, and the output The present invention is characterized in that an output one frame period monitoring means for outputting a switching control signal to the switch means is provided. This makes it possible to provide a scanning frequency conversion method that can convert any scanning frequency.

Industrial applications The present invention relates to a scanning frequency conversion method.

In recent years, image information has been provided in a wide variety of ways, such as TVs, personal computers, captains, etc., and the reality is that the scanning frequencies of these displays are different. For example, the scanning frequency of a TV is 30 Hz, while the frequency of a personal computer is generally 60 Hz. Conventionally, scanning frequency conversion devices (scan converters) have been developed to meet the demand for viewing image information having different scanning frequencies on a single display.

Prior Art A conventional scanning frequency conversion system is shown in FIG. Figure 8 (A
) and (B), the conventional scanning frequency conversion method generates an output image signal by increasing the scanning frequency of the input image signal by just twice. That is, by reading the same image data twice in one horizontal scanning period of the input image signal, the scanning frequency is doubled.

FIG. 9 shows a conversion circuit used in such a conventional scanning frequency scan conversion method. The input image signal is one horizontal scan (
IH) 2 by the input switch 12 switching to 1a.
1 horizontal scanning memory (1 memory > 10a, 10b
stored in either. The switching of the input switch 12 is performed by detecting a horizontal synchronizing signal of the input image signal by a one horizontal scanning (1H) period detection circuit 14, and controlling switching of the input switch 12 based on this.

The horizontal synchronization signal of the input image signal detected by the 1H1 period detection circuit 14 is input to the output switch 16 via the inverter 18, and thereby the input switch 12
When the input image signal is written into the 111 memory 10a, the contents of the other 111 memory 10b are read out via the output switch 16. That is, the output synchronization signal generation unit 20 generates a synchronization signal with a frequency twice that of the input image signal, and thereby the image data of the 1H memory that is not currently being written is read out twice and the output image is generated. &
I am trying to output it as a signal.

As a result, as shown in FIG. 8, the input image signals are
, c, d, then a, a, b, b, c.

Output image signals such as c, d, and d can be obtained.

Problems to be Solved by the Invention As mentioned above, according to the conventional frequency conversion method, by converting the input frequency to twice the scanning frequency, it is not suitable for viewing, for example, a television image on a personal computer display. was. However, according to this conversion method, the scanning frequency is simply doubled, so it cannot be converted to an arbitrary scanning frequency, and cannot be applied to all displays that use different scanning frequencies. There was a problem.

The present invention has been made in view of these points, and its purpose is to provide a scanning frequency conversion method that can support any scanning frequency.

Means for Solving the Problems FIG. 1 shows a diagram of the principle of the present invention. The input switch means 3 is connected to first and second frame memories 1 and 2 that store one frame of input image signals. Further, the first and second frame memories 1.2 are connected to an output switch means 4, and the data of the first and second frame memories 1, 2 are outputted as output image signals via the output switch means 4.

An output one frame period monitoring means 5 is connected to the output switch means 4, and the output one frame period monitoring means 5
The output switch means 4 is switched to 1/7 by the switching control signal.

By switching and controlling the input switch means 3, the input image signal is selectively output to the first frame memory 1 or the second frame memory 2. The output one frame period monitoring means 5 counts the number of times the input switch means 3 is switched during one frame period of the output signal, and outputs a switching control signal to the output switch means 4 as follows. That is, when the number of switching of the input switch means 3 counted by the output one frame synchronization monitoring means 5 is an odd number, the output switch means 4
, and in the case of an even number of times, the output switch means is controlled not to be switched.

By reading out the data in the first frame memory 1 or the second frame memory 2 using a synchronization signal having a target frequency while switching and controlling the output switch means 4 in this way, the scanning frequency of the input image signal can be changed to an arbitrary scanning frequency. can be converted into an output image signal having .

Note that the even number of times used in this specification is defined to include 0.

Embodiment FIG. 2 shows a scanning frequency conversion circuit according to an embodiment of the present invention, in which an input image signal is stored in one of two one-frame memories 22a and 22b by an input switch 12 that is switched every frame. . Switching control of the input switch 12 is achieved by detecting the vertical synchronization signal of the input image signal using the one frame period detection circuit 24. Switching of the output switch 16 when reading data stored in the one-frame memories 22a and 22b is controlled by the output one-frame period monitoring circuit 26. That is, the output one-frame period monitoring circuit 26 receives the vertical synchronization signal of the input image signal detected by the one-frame period detection circuit 24 and the output vertical synchronization signal generated from the output synchronization signal generation section 28. , counts the number of times the input switch 12 is switched in one frame period of the output signal, and if the number of switches is an even number including O, the output switch 16 is not switched, and if the number of switches is an odd number, the output switch 16 is not switched. control to switch.

While controlling the output switch 16 in this manner, the vertical interval I! is generated by the output synchronization signal generation section 28! ll
1 frame memory 22a according to the signal.

Alternatively, by reading the data of 22b, the scanning frequency of the input image signal can be converted into an output image signal having an arbitrary scanning frequency without reducing the resolution.

Referring now to FIG. 3, a detailed diagram of the output one frame period monitoring circuit 26 is shown. The present monitoring circuit 26 is constituted by two flip 70 tabs 30,32. The flip-flop 30 counts the number of times the input switch 12 is switched, and outputs the result from 01. The output vertical synchronization signal generated by the output synchronization signal generation section 28 is input to the reset terminal R of the flip 70 tube 30 via the signal delay circuit 34. Therefore, each time one frame is output, the output Q1 of the flip-flop 30 becomes L level. The input vertical synchronization signal of the input image signal detected by the one frame period detection circuit 24 is input to the clock terminal CLK of the flip 70 tube 30, and the data terminal is connected to Ql.

As is clear from this circuit configuration, the clock terminal CLK
The output of Ql changes as follows depending on the input line of the vertical synchronization signal input to the Ql.

Even number of times including O...Q1 output low level Odd number of times...Q1 output high level Next, a switching control signal generation circuit using a flip-flop 32 for J- will be described. The 01 output of the flip-flop 30 is input to the J and 98 children of the flip-flop 32, and the output vertical synchronization signal is input to the clock terminal CLK.

Further, the reset terminal R and set terminal S of the flip-flop 32 are fixed at a high level.

The flip-flop 32 at J- is at L level depending on the value of J at the time of clock input.The output does not change and J=
K = 1-Level...The output changes when it is inverted.

Therefore, depending on the value of the 01 output of the flip 70 knob 30 when the output vertical synchronization signal is input to the clock terminal CLK, the value of the switching control signal for one frame period output from the 02 of the flip 70 knob 32 is as follows. become.

Table 1 By inputting the switching control signal output from the flip-flop 32 to the output switch 16, the input switch 1
The output switch 16 is controlled to switch as described above according to the number of times of switching.

FIG. 4 is a detailed diagram of the frame memories 22a and 22b and the output synchronization signal generation section 28. The output pixel frequency generation circuit 36 generates a frequency corresponding to one pixel, and output addresses are generated based on this frequency. A counter 38 generates an address to be read from one frame memory 22a or 22t). This counter 38 is configured so that the counter value is reset by the vertical synchronizing signal generated by the output horizontal/vertical synchronizing signal generation/frequency dividing circuit 40 and starts counting from 1 every frame.

An output address is connected to one of the one-frame memories 22a and 22b by the output switch 16, and output image data is read out according to this address and sent to a display device such as a CRT (not shown) via the output switch 16. .

In order to easily realize the above-described configuration, it is desirable to employ two-board memories for the one-frame memories 22a and 22b.

The operation of this embodiment will be explained below with reference to the time chill rates shown in FIGS. 5 to 7.

FIG. 5 shows a time chart when the input scanning frequency is equal to the output scanning frequency, and the output frames of the output image signal are A, B;
C... are switched in good order.

Figure 6 shows a time chart when the output scanning frequency is greater than the input scanning frequency, and in this case, the third
When the output vertical synchronizing signal is input to the output terminal CLK of the flip-flop 32 at J- shown in the figure, the flip-flop 7
When the 01 output of the 0 tube 30 is at the L level, the switching control signal does not change, so the output switch 16 is not switched, and the same image data stored in the same frame memory is continuously output. That is, in FIG. 6, frame data C and F at such timing
will be output twice in a row.

FIG. 7 shows a time chart when the input scanning frequency is higher than the output scanning frequency. In this case, for example, if frame A is stored in the 1-frame memory 22a, this frame A is read out. During this time, the input switch 12 is switched to write frame B to the 1-frame memory 22b, but the output switch 16 is not switched during this time, and the input switch 12 is switched to write frame C to the 1-frame memory 22a. become. Since the output switch 16 is still connected to the one frame memory 22a, frame C will be read out following frame A, and frame B will not be output. In this way, frames B and F in FIG. 7 are dropped, but the resolution is not reduced.

As is clear from the above explanation, in the scanning frequency conversion method of the present invention, there are cases in which the same frame is output continuously, and there are cases in which a specific frame is not output, but the actual frame frequency is a value of several tens of H2. Therefore, when viewed by humans, increases and decreases in frames cannot be discerned, and there is no particular problem because they are regarded as continuous frames.

Effects of the Invention Since the scanning frequency conversion method of the present invention is configured as detailed above, it has the effect of converting the scanning frequency of an input image into an output image having a desired scanning frequency without causing resolution deterioration.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of a scanning frequency conversion circuit according to an embodiment of the present invention, Fig. 3 is a detailed diagram of a one-frame period monitoring circuit for output, and Fig. 4 is a frame memory and output synchronization circuit. A detailed diagram of the signal generation section. Figure 5 is a time chart when the input scanning frequency and output scanning frequency are equal. Figure 6 is a time chart when the output scanning frequency is greater than the input scanning frequency. Figure 7 is a time chart when the output scanning frequency is greater than the input scanning frequency. A time chart when the input scanning frequency is higher than the output scanning frequency, FIGS. 8A and 8B are explanatory diagrams of a conventional conversion method, and FIG. 9 is a diagram of a conventional scanning frequency conversion circuit. 12...Input switch, 16...Output switch, 2
2a, 22b-1 frame memory, 24...1 frame period detection circuit, 26...1 frame period monitoring circuit for output, 28...
Synchronous signal generator for output.

Claims (1)

[Scope of Claims] First and second frame memories (1, 2) for storing one frame of an input image signal; and said first and second frame memories (1, 2) for storing one frame of an input image signal.
2) input switch means (
3); an output switch means (4) for switching and controlling reading of data stored in the first and second frame memories (1, 2);
), and the output switch means (4) counts the number of times the switch is switched.
and an output frame period monitoring means (5) for outputting a switching control signal to the output frame period monitoring means (5), when the number of switching of the input switch means (3) counted by the output frame period monitoring means (5) is an odd number. A scanning frequency conversion system characterized in that the output switch means (4) is controlled to be switched in the case of an even number of times, and not to be switched in the case of an even number of times.