JPS6326587B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a color image signal encoding device that compresses color image signals through encoding to reduce transmission time or storage memory capacity. One of the conventional encoding methods for color image signals is the mode run length encoding method. This is to encode a color image signal using a run length code that specifies the length of the run and a mode code that specifies the color of the run, when a continuation of the same color in a color image signal is called a run. In the mode run-length encoding method, a mode code and a run-length code are determined according to the appearance frequency of each color and each run length. However, these codes are determined without regard to the correlation between different colors, such as the fact that orange is more likely to appear next to yellow, and cannot be said to be a very efficient encoding method. An object of the present invention is to provide an efficient color image signal encoding device that takes into account the correlation between different colors. According to the present invention, the already input N(2 ^n-1 <
N2 ⁿ ) means for arranging N signal values for predicting the next input image signal x based on the color image signal S of the color in order of prediction accuracy, and the actual signal values of the image signal x being arranged in the order of the predicted accuracy; a means for detecting the rank of the signal value, and at most n prediction error signals e _i (1in) corresponding to the rank;
means for predictively encoding the image signal x by generating a mode signal M _i indicating the high probability that each prediction error signal e _i (1in) is 0, i=1
In this case, means for generating based on the color image signal S and i-1 prediction error signals e _j (1ji-1), and means for generating each prediction error signal e _i (1in)
and the corresponding mode signal M _i (1in)
There is obtained a color image signal encoding device having means for compression encoding after grouping based on the following. The present invention will be explained in detail below using the drawings. FIG. 1 is a block diagram of an encoding apparatus according to the present invention. A predictive encoding circuit 2 inputs a color image signal 1 obtained by photoelectrically converting a color image, predicts an image signal x currently being input based on a reference image signal S, and transmits the prediction error signal 3 to a compression encoding circuit. Send to 4. Further, the predictive encoding circuit 2 and the compression encoding circuit 4 are controlled by the control circuit 6.
An example of the reference image signal S is shown in FIG. In FIG. 2, the dotted line indicates the main scanning line of the image, along which the image is scanned from left to right, and when the right end is reached, scanning continues from the left end of the main scanning line below.
A, b, c, d indicated by circles are reference image signals S
These are the four pixels that make up the image. x indicated by a double circle is the image signal of interest, and x is predicted based on the reference image signal S = (a, b, c, d) scanned before x, and its prediction error is compressed and encoded. Ru. Second
In the figure, the number of pixels composing S is four, but there are five and six pixels.
The S may be made up of a larger number of pixels, or the S may be made up of fewer pixels, such as three pixels a, b, and c excluding d. However, if the number of pixels constituting S is too small, the encoding efficiency will decrease, and if it is increased, the scale of the predictive coding circuit will become unnecessarily large. Hereinafter, S is a, b, adjacent to x, as shown in Figure 2.
The explanation will be given assuming that it consists of 4 pixels c and d. Returning to FIG. 1, the explanation will be continued. The prediction error encoding circuit 4 compresses and encodes the prediction error signal 3 and outputs it as a prediction error encoded signal 5. The control circuit 6 sends out clock signals, control signals, and synchronization signals to control each circuit. Figure 3 shows eight colors (black, red, orange, yellow, purple, blue, green,
Predictive encoding circuit 2 for color image signals (white)
FIG. 2 is a block diagram showing one embodiment of the invention. As already mentioned, S is assumed to consist of the four pixels a, b, c, and d shown in FIG. 2, and each color is expressed as a 3-bit binary number as shown in the center column of Table 1. The right column of Table 1 shows it in decimal notation. Of course, by expanding this example, it is possible to configure a circuit for S consisting of a large number of pixels and a color image signal having even more colors.

[Table] In this predictive encoding circuit, the 3-bit color image signal 1 is 3(l+2) as shown in Figure 3.
The signal is input to the bit shift register 7. Here, l represents the number of pixels per main scanning line. Ranking determination
ROM8 is a, b, c, d4 from shift register 7
Input pixels (3 bits for each pixel) as address data, and based on that, select the color with the highest probability of matching x with α ₁ (3 bits), the color with the second highest probability of matching with α ₂ (3 bits), Similarly, the colors with a high probability of matching from 3rd to 8th are α ₃ , α ₄ , α ₅ , α ₆ , α ₇ , α ₈
(3 bits each), data (3 x 8 bits)
Output as . The rank signal selection circuit 9 selects α _i (i
=1 to 8) and x are input, _aix that matches x is detected, _ix -1 is expressed in 3 bits, and output as _e1 , _e2 , and _e3 . Hereinafter, e _i will be referred to as the i-th bit prediction error signal. In this way, the prediction error signal e _i (i=1 to 3)
If , the probability that each e _i is 0 is always higher than the probability that it is 1, and each e _i becomes a signal suitable for one-dimensional run-length encoding. Also, since each e _i is generated based on S and x,
This circuit is a predictive encoding circuit that fully utilizes the correlation between S and x. Since S and x are generally different colors, this circuit is a predictive encoding circuit that utilizes the correlation between different colors. S = (a, b, c, d) is S ₁ = (4, 3, 4,
5) and S ₂ = (2, 7, 6, 1) will be specifically explained. Here, pixels a, b,
The colors c and d are shown in decimal numbers, and the relationship between colors and decimal numbers is shown in Table 1. Let P(x|S) be the conditional probability that the image signal of interest is x when the reference image signal is S, and P(x|S ₁ ) and P(x|S ₂ ) are shown in Tables 2 and 5, for example. Let's say it's like this. Figure 4,
These are shown graphically in FIG. P
(x|S ₁ ) is unimodal, and P(x|S ₂ ) is bimodal. Tables 3 and 6 show α ₁ and P(α _i |S _j ) for S=S _j (j=1, 2). α _i is determined such that P(α _i |S _j ) decreases as the number i increases. Here, P(α _i |S _j ) is the conditional probability that the target image signal x=α _i when the reference image signal S=S _j . If x is expected to occur with exactly the same probability for two or more levels, the higher level is associated with α _i having a smaller subscript number. Ranking determination
ROM8 is based on S=S _j (j=1, 2), and the third
As shown in Table 6, α _i (i ₌ 1~
8) is output. The selection circuit 9 is α _i (i=1 to 8)
and x, and when S=S _j (j=1, 2), the second
As shown in Table 5, e=(e ₁ , e ₂ , e ₃ ) is determined.
In Tables 2 and 5, i is P(x|S _j ) is S=
S _j indicates the i-th largest prediction error.

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[Table] Number e is equal to i-1. For example, S=S ₁ , x=5
Then, as shown in Table 3, x matches α ₂ =5, which has the second largest conditional probability P (α ₂ | S ₁ ) = 0.20, so as shown in Table 6, e = i _x −1=
2-1=1=(0, 0, 1) is output from the selection circuit 9 as a prediction error signal. S=S _j (j=1,
2), from Tables 2 and 5, each bit e _i of e
The probability that (i = 1 to 3) is 0 or 1 is P(e _i |
S _j ) (i=1 to 3, j=1, 2) can be calculated as follows. P (e ₁ = 0 | S _j ) = ₄ 〓 ⁱ⁼¹ P (α _i | S _j ) P (e ₁ = 1 | S _j ) = 1-P (e ₁ = 0 | S _j ) P (e ₂ = 0 | S _j ) = ₂ 〓 ⁱ⁼¹ P (α _i | S _j ) + ₆ 〓 ⁱ⁼⁵ P (α _i | S _j ) P (e ₂ = 1 | S _j ) = 1-P( e ₂ = 0 | S _j ) P ( e ₃ = 0 | S _j ) = P ( α ₁ | S _j ) + P ( α ₃ | S _j ) + P ( α ₅ | S _j ) + P ( α ₇ | S _j ) P( _e3 =1| _Sj )=1-P( _e3 =0| _Sj ) Tables 4 and 7 show the calculation results. Fourth
In Table 7, the probability that each e _i (i=1 to 3) becomes 0 is always higher than the probability that it becomes 1. e _i (i=1
The reason why ~3) has such a property will be explained below using the case of S=S ₂ as an example. Figure 6 a,
_The probability P( _{α 1}
|S ₂ ) (i=1 to 8) is shown in a graph with α _i on the horizontal axis. Graphs a, b, and c are all the same, but the diagonal lines are drawn differently. The meaning of the shaded portion will be explained later. In Fig. 5, the probability of occurrence of x when S = S ₂ P(x|S ₂ ) (X = 0 to 7) is graphed with x as the horizontal axis. x｜
Figure 6 a, b, and c are obtained by rearranging S ₂ ) in descending order of magnitude to the left. P(x|S ₂ ) had a bimodal distribution, but P(α _i |S ₂ ) was rearranged from the left in descending order of magnitude, resulting in a downward-sloping distribution. As is clear from the method of creation, P(x|S)
In general, P(α _i | S) no matter what type of distribution
is monotonically decreasing with respect to the index i of α _i , and P(α _i | S)
has a downward-sloping distribution. The explanation is given using the case of S=S ₂ as an example, but the following explanation is based only on the fact that P(α _i | S) has a downward-sloping distribution, so it holds true for the general case of S. do. Therefore, the shaded area (x=α ₁ to α ₄ , e=0 _{to 3} , corresponding to e ₁ =0) in FIG.
~7, which corresponds to e ₁ = 0), so e ₁ = 0
The probability of e 1 =1 is higher than the probability of e ₁ =1. Similarly, Figure 7b
The shaded part (x=α ₁ , α ₂ , α ₅ , α ₆ , e=0, 1,
4, 5 (corresponding to e ₂ = 0) are blank parts (x =
α ₃ , α ₄ , α ₇ , α ₈ , e=2, 3, 6, 7 or e ₂
= 1), so the probability of e ₂ = 0 is e ₂ = 1
higher than the probability of Furthermore, the shaded area in Figure 7d (x=
α ₁ , α ₃ , α ₅ , α ₇ , e=0, 2, 4, 6 or e ₃
= 0) are blank parts (x = α ₂ , α ₄ , α ₆ , α ₈ , e
=1, 3, 5, 7, that is, e ₃ =1), so the probability of e ₃ =0 is higher than the probability of e ₃ =1. The above shows that the probability that e _i (i=1 to 3) is always 0 is higher than the probability that it is 1. The method of generating the error signals e ₁ , e ₂ , e ₃ has been explained above, and next, the first, second, and third mode signals M ₁ ,
Let's explain how M ₂ and M ₃ are generated. Until now, we have considered the probabilities regarding e ₁ , e ₂ , and e ₃ based only on the reference image signal S, but from now on, we will consider e ₁ in addition to S for e ₂ , and S for e ₃ . Besides e ₁ ,
Let's renormalize and consider e ₂ as a condition. These newly devised conditional probabilities are shown in Tables 8 to 10 when S=S ₁ , and Tables 11 to 13 when S=S ₂ . In these tables, P(e ₁ | S _j ), P(e ₂
|S _j , e ₁ ) and P(e ₃ |S _j , e ₁ , e ₂ ) (j=1, 2) have the following meanings. P(e ₁ |S _j ): Probability that the prediction error signal of the first bit is e ₁ when the reference image signal S is S _j . P(e ₂ | S _j , e ₁ ): Reference image signal S is S _j and the first
The probability that the second bit's prediction error signal is _e2 when the bit's prediction error signal is _e1 . P(e ₃ | S _j , e ₁ , e ₂ ): When the reference image signal S is S _j and the prediction error signal of the first bit is e ₁ and the prediction error signal of the second bit is e ₂ , the third bit The probability that the prediction error signal of is e ₃ . The above probabilities are P(α _i | S ₁ ) and P in Tables 3 and 6.
It is calculated from (α _i |S ₂ ) as follows. The conditional probabilities calculated in this way are illustrated in FIGS. 7a, b, and c for the case of S=S ₂ . Using Figure 6, P(e ₁ | S ₂ ), P(e ₂ | S ₂ , e ₁ ), P(e ₃ |
Let us intuitively explain S ₁ , e ₁ , e ₂ ). P(e ₁ | S ₂ ): P(0 | S ₂ ) is when S=S ₂ and x is α ₁ ,
Probability of being either α ₂ , α ₃ , or α ₄ . That is, the sixth
In figure a, the percentage of the shaded area relative to the whole. P(1|S ₂ ) is when S=S ₂ and x is α ₅ , α ₆ , α ₇ ,
Probability of being one of _α8 . That is, the proportion of blank space to the whole in Fig. 7a. P(e ₂ | S ₂ , e ₁ ): P(0 | S ₂ , 0) is when S=S ₂ and x is one of α ₁ , α ₂ , α ₃ , α ₄ Probability of either α ₁ or α ₂ . That is, the proportion occupied by the shaded area in the left half of the dotted line in Figure 7a. P(1|S ₂ , 0) is the same condition when x is α ₃ , α ₄
Probability of either. In other words, the proportion of blank space in the same part. P(0|S ₂ , 1) is S=S ₂ and x is α ₅ ,
Probability that x becomes either α ₅ or α ₆ when α ₆ , α ₇ , or α ₈ . In other words, the proportion occupied by the shaded area in the right half of Figure 6a bordering on the dotted line. P(1|S ₂ , 1) is the same condition when x is α ₇ , α ₈
Probability of either. In other words, the proportion of blank space in the same part P(e ₃ | S ₂ , e ₁ , e ₂ ): P (0 | S ₂ , 0, 0) is S
= S ₂ and the probability that x becomes α ₁ when x is either α ₁ or α ₂ . That is, the proportion occupied by the shaded area in the part consisting of α ₁ and α ₂ in Figure 6c. P(1 | S ₂ , 0, 0) is when x is α ₂ under the same conditions
Probability of becoming . In other words, the proportion of blank space in the same part. P(0|S ₂ , 0, 1), P(0|S ₂ , 1, 0), P
(0 | S ₂ , 1, 1) are respectively shown in Figure 6C, α ₃
and the proportion occupied by the shaded area in the part consisting of α ₄ , α ₅ and α ₆ , α ₇ and α ₈ , P (1 | S ₂ , 0, 1), P (1 | S ₂ , 1, 0), P
(1 | S ₂ , 1, 1) is the proportion of blank space in each part. The mode signal M _i has the conditional probabilities P(e ₁ | S), P(e ₂ | S, e ₁ ), P(e ₃ | S,
e ₁ , e ₂ ), it is determined as follows. M _i : 0 if P(0|S) is equal to or greater than the given probability Pθ, 1 if smaller M ₂ : P(0|S, e ₁ ) is equal to or greater than the given probability Pθ 0 when P(0|S, e ₁ , e ₂ ) is equal to or _greater than the given probability Pθ, 1 when smaller Tables 14 and 15 show that S=S ₁ , mode signal when S ₂
A list of M _i was posted. These are Tables 8 to 10.
Pθ based on the conditional probabilities in Tables 11 to 13
=0.7. The method for determining the mode signal M _i includes the conditional probabilities P(e ₁ | S), P(e ₂ |
There is also a method using P(e ₃ |S), but as will be seen later, this method can achieve more efficient encoding.

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[Table] Let us return to the predictive encoding circuit 2 in FIG. 3 and continue the explanation. Figure 3 shows 1st, 2nd, and 3rd mode signal generation.
The first, second and third mode signals M ₁ , M ₂ and M ₃ are created by the ROMs 15, 16 and 17, which are based on the method explained in detail above, and M ₁ is
The reference image signal S=(a, b, c,
d), M ₂ is determined by the ROM 16 using the reference image signal S = (a, b, c, d) and e ₁ , and M ₃ is determined by the ROM 17 using the reference image signal S' = (a , b, c, d) and e ₁ , e ₂ . P(e ₁ | S), P(e ₂ | S), P(e ₃ |
If we decide to determine M ₁ , M ₂ , M ₃ using S), e ₁ and e ₂ will become unnecessary input data in the ROMs 16 and 17, and the predictive encoding circuit 2 will have a simpler circuit configuration. As we will see later, the encoding efficiency decreases. Although the case of 8 colors and 4 pixel reference has been described above, it is generally easy to extend this to the case of N (2 ^{n -1} <N2 ⁿ ) colors and m pixel reference. At this time, in the predictive encoding circuit 2 of FIG. 3, the ROM 8 inputs m n-bit pixels as address data, and outputs α _i (1iN) consisting of n bits as N data. The selection circuit 9 selects α _i (1iN) and n
It inputs x consisting of bits and outputs at most n 1-bit prediction error signals e _i . The reason why there are at most n pieces here is as follows. For example, assume that in a seven-color image signal, x can take on colors corresponding to 0, 1, . . . , 6. Since N=7, n=3, and α ₈ corresponds to a color that never occurs as x. For example, if α ₈ = 7, then x = α ₈ = 7, so e
≠(1, 1, 1). Therefore, when e ₁ =e ₂ =1, e ₃ is always 0, and there is no need to generate the third bit prediction error signal e ₃ at this time. Like this N
When ≠2 ⁿ , it is not necessary to always generate an n-bit prediction error signal. In addition, in general N(2 ^n-1 <N
2 ⁿ ) value, the ROM for mode signal determination is each e _i (i=
1 to n), and each outputs a mode signal M _i (i=1 to n). For M ₁ determination
ROM determines M ₁ using only S, and for determining M ₁
ROM (i=2 to n) is M _i using S and e ₁ to e _i-1
Determine. Next, a compression encoding circuit that encodes the prediction error signal obtained as described above will be explained. Predictive encoding circuit 2 in FIG.
The outputs e ₁ , e ₂ , e ₃ of the predictive encoding circuit 2 shown in the figure
is added to the compression encoding circuit 4 of FIG. If a one-dimensional run-length encoding circuit is used as the compression encoding circuit 4, e ₁ , as shown in FIG.
The first idea is to serially connect e ₂ and e ₃ to form a one-dimensional signal sequence and perform run-length encoding. In FIG. 8, e ₁ , e ₂ , and e ₃ are written from left to right in the order of occurrence. As already explained in detail, the probability that e ₁ , e ₂ , and e ₃ will always be 0 is higher than the probability that they will be 1, so data compression is possible even in this case. However, more efficient encoding can be performed using a mode signal indicating a high probability that the prediction error signal becomes 0 (for example, Japanese Patent Laid-Open No. 79610/1983, calligraphic communication system). The feature is that the prediction accuracy is high when the reference image signal has a certain pattern and low when it is a certain pattern, and the prediction error signal is divided into a group with a high accuracy rate and a group with a low accuracy rate based on the reference image signal. This method divides the data into two groups and performs encoding appropriate for each group to achieve a higher compression rate. If we consider that the prediction accuracy means that each e _i (i=1 to 3) becomes 0, this can be applied to the present invention.
At this time, in addition to the prediction error signals e ₁ , e ₂ , and e ₃ , the predictive encoding circuit 2 in FIG.
It is necessary to output M ₁ , M ₂ , and M ₃ . Figure 3
Output data of ROM15, 16, 17 M ₁ , M ₂ ,
M ₃ (1 bit each) is this mode signal, e ₁ ,
It is added to the encoding circuit 4 along with e ₂ and e ₃ . What should be noted in FIG. 3 is that the second mode signal generation ROM 16 uses _e1 in addition to the reference image signal, and the third mode signal generation ROM 17 uses _e1 and _e2 . This is the essential difference between the present invention and conventional binary image signal encoding devices (for example, Japanese Patent Application Laid-open No. 79610/1983, calligraphic communication system). Of course, in the multilevel image signal encoding device, all mode signals may be determined using only the reference image signal as in the conventional binary image signal encoding device, but as will be explained later, the encoding Efficiency decreases.
When using the mode signal in this way, the compression encoding circuit ₄ in FIG.
Considering that the prediction error signal e _i has a high probability of being 0, a relatively short code is generated even for a long 0 run. For the prediction error signal e _i with M _i =1, a long code is generated for a long 0 run, taking into account that the probability of it being 0 is not so high. If a mode signal is not used, e _i with a high probability of being 0 and e _i with a low probability of being 0 are encoded together, but if a mode signal is used, those with a high probability of being 0 and those with a low probability of being 0 are encoded together. It can be separated and efficiently compressed and encoded. FIG. 9 shows a specific example of the coding order of e ₁ , e ₂ , and e ₃ when using a mode signal. 9th
In the figure, each e _i and M _i are written from left to right in the order of occurrence, e i surrounded by a solid _line corresponds to M _i =0, and e _i surrounded by a dotted line corresponds to M _i = This corresponds to 1. The arrows indicate the encoding order of e _i . The first arrow indicates that the e _i 's surrounded by solid lines are serially connected and encoded in the order of their occurrence, and in the case of e _i's that are generated at the same time, in ascending order of numbers, and the second arrow is surrounded by dotted lines. This shows that e _i are serially connected in the same order and encoded. In this way, if we decide to encode the second bit prediction error signal e ₂ after e ₁ and the third bit prediction error signal e ₃ after e ₁ and e ₂ , the encoding of e ₂ is not only S but also encoded e ₁ prior to e ₂ , e ₃
For encoding, not only S but also e ₁ and e ₂ encoded prior to e ₃ can be used. Therefore, the mode signal M ₂ indicating the high probability that e ₂ becomes 0 is not only S but also
It is advantageous to determine the mode signal M ₃ using e ₁ and to indicate the high probability that e ₃ becomes 0, using not only S but also e ₁ and e ₂ . For example, if S=S ₁ and each mode signal M _i is determined by S only, then
Get 16 tables. From Table 4, this is the boundary probability Pθ=
It was calculated as 0.7. As can be seen by comparing this with Table 14, which uses not only S but also e ₁ and e ₂ to determine the mode signal, there is no difference in M ₁ since both are determined only by S, but M ₂ In Table 16, it is 1 regardless of e ₁ , whereas in Table 14, it is 0 when e ₁ is 0, and 1 when it is 1, and it is determined more precisely by dividing the cases. Similarly, M ₃ is in table 16
It is 1 regardless of e ₁ and e ₂ , but in Table 17, it is 1 when e ₁ is 0 and e ₂ is 0, 0 when e ₁ is 0, e ₂ is 1, e ₁ is 1, 1 when e ₂ is 0, e ₁ is 1, e ₂ is 1
The value is 1 when It is better to define each M _i more precisely, so that e _i
Since grouping by M _i is more effective and gives higher coding efficiency, not only S but also e ₁
Alternatively, it can be seen that e ₂ should be used to determine the mode signals M ₂ and M ₃ . Table 17 shows an example in which each mode signal M _i is determined only by S when S=S ₂ . This was obtained from Table 7 using the boundary probability Pθ = 0.7. As in the case of S=S ₁ , compare Tables 15 and 17. FIG. 10 is a block diagram showing one embodiment of the compression encoding circuit 4. In this circuit, as shown in FIG. 9, e _i is coded separately into one corresponding to M _i =1 (encircled by a dotted line) and one corresponding to M _i =0 (enclosed by a solid line).
Further, in this circuit, "run per prediction + predicted error pixel" is defined as one run, the run length is set as "e _i =0 length", and the run length is encoded. It should be noted that when the encoding procedure is determined as described above, one run generally consists of three types of error signals e ₁ , e ₂ , and e ₃ . Roughly speaking, the circuit in Figure 10 consists of two parts, upper and lower, with e _i corresponding to upper part M _i =1.
is a run encoding circuit consisting of , while the bottom part is
This is a run encoding circuit consisting of e _i corresponding to M _i =0. In Fig. 10, e ₁ , e ₂ , e ₃ , M ₁ , M ₂ ,
_M3 is first set in 3-bit registers 38 and 39. The selection circuits 76 and 77 first select one each of e ₁ and M ₁ , and then select one each of e ₂ and M ₂ .
Finally, select one each of e ₃ and M ₃ . After e ₁ , e ₂ , e ₃ and M ₁ , M ₂ , M ₃ are selected one by one, the next e ₁ , e ₂ e ₃ and M ₁ , M ₂ , M ₃ are selected.
is set in the 3-bit registers 38 and 39, and the same operation is repeated. e _i is inverted by the NOT circuit 78, and when M _i =1 (H level), it is added to the counter 83 via the AND circuit 81, and M _i =
When the signal is 0 (L level), it is inverted by the NOT circuit 80 and added to the counter 87 via the AND circuit 82. The counter 83 receives the signal from the AND circuit 81 at H level, that is, M _i =1 (H level), e _i =0
(L level), counts up. The run end detection circuit 86 outputs a pulse signal RCS1 when e _i becomes H level, sets the contents of the counter 83 in the run length code generator 84, and then outputs the pulse signal RCS1.
Clear 3. The value set in the run length code generator 84 indicates the length for which e _i corresponding to M _i =0 remains 0, which is the run length to be encoded. The run-length code generator 84 generates a run-length code RLC1 corresponding to the set value, and outputs a pulse signal RCE1 after the generation of RLC1 is completed. The input inhibit circuit 57 is set by the RCS1 signal.
The flip-flop is reset by the RCE1 signal, and its output signal IHB1 is applied to registers 38 and 39 through an OR circuit 52. The IHB1 signal is high when the run-length code generator 84 is outputting the code RLC1.
When registers 38 and 39 receive INHB at H level, they temporarily stop inputting e _i and M _i during that time. For e _i for M _i =0, the counter 87, run length code generator 88, run end detection circuit 90, and input inhibit circuit 58 perform similar operations, and the run of e _i for M _i =1 is performed. detect,
Encode the run length. Run length code generator 88 generates relatively short codes for long runs compared to code 84 to provide efficient encoding. Care must be taken in the output order of the run-length codes RLC0 and RLC1 generated from the run-length code generators 84 and 88. If the run-length codes were simply output from the present encoder in the order in which they were generated from the run-length code generators 84 and 88, the decoder would be unable to decode them. To enable decoding, it is necessary to focus on the signal e _i located at the beginning of each run, and generate the run-length code for each run in the order in which the leading signal is taken in from the prediction circuit, that is, in the order in which each run occurs. . In FIG. 10, the run-length code generator 8
The circuit centered on the part marked on the right side of 4.88 controls the output order of this run-length code. The operation will be specifically explained in detail using the time chart shown in FIG. In FIG. 11, K written at the top indicates the order in which the prediction error signal e _i and mode signal M _i written below are input for convenience of explanation below. Since the signal input is performed intermittently, K is not always updated at regular intervals, and is not updated while the run-length code generators 84 and 88 are generating run-length codes. The signals other than K in FIG. 11 are shown on the circuit of FIG. 10, but each signal will be explained below. e _i and M _i are selection circuits 7
COU1 and COU0 are the output signals of counters 83 and 87 and indicate the respective count values. RCS1 and RCS0 are pulse signals output from the run end detection circuits 86 and 90 and indicate run detection. RLC1 and RLC0 are the output codes of run-length code generators 84 and 88, and RCE1 and RCE0
is a pulse signal indicating the end of generation of run-length codes RLC1 and RLC0 output from run-length code generators 84 and 88. IHB1 and IHB0 are outputs of the input inhibiting circuits 57 and 58, and are signals indicating that the run-length code generators 84 and 88 are generating run-length codes. REDM is a signal output from the flip-flop 44 indicating that the contents of the code memory 43 are being read. INHB is
When this signal is at H level at the output of the OR circuit 52, the registers 38 and 39 are e ₁ , e ₂ , e ₃ , M ₁ , M ₂ , M ₃
Pause input. SWCH is the output of the switch signal generation circuit 41. When this signal is at H level, RLC1 and RLC0 are applied to the selection circuit 46 and memory 43, respectively, via the switch circuit 42, and when this signal is at L level, the connection is reversed. Become. RLCE
is the output signal of the selection circuit 40, which is the same as RCE1 when SWCH is at H level, and the same as RCE0 when SWCH is at L level. RLCD is the output signal of this encoding circuit. When REDM is at the H level, the run-length code read from the run-length code memory 43 is selected by the selection circuit 46 as the RLCD, and when REDM is at the L level, the run-length code generated from the run-length code generator 84 or 88 is selected. is directly selected as the RLCD by the selection circuit 46 without going through the memory 43. Although each signal has been roughly explained above, specific changes in each signal will be explained in accordance with the time chart of FIG. 11. In FIG. 11, when K=5, e _i =1 and the end of the run occurs only when e i =1. At this time, M _i =0, so this run is M _i =
It is for 0. The run length is counted by the counter 87 as COU0=2. When K=5, e _i =1, M _i =0, so AND circuit 9
The output of No. 4 is at H level. Run end detection circuit 9
0 receives this and generates RCS0, sets the contents of the counter 87, COU0=2, in the run-length code generator 88, and immediately resets the counter 87. RCS0 also sets the input inhibit circuit 58.
Set INHB to H level according to IHB0 to H level,
The input of the prediction error signal e and the mode signal M to the registers 38 and 39 is temporarily prohibited. The run-length code generator 88 generates a run-length code RLC0=C2 corresponding to COU0=2, and since SWCH is at H level, it is written to the run-length code memory 43 via the switch circuit 42, and after the writing is completed, RCE0
is generated and the input inhibit circuit 58 is reset. What should be noted here is that the run length code C2 that occurs for the first time is immediately converted to the output signal RLCD of this encoding circuit.
This is because the data is temporarily written into the memory 43 without being output as a file. This is based on the already mentioned principle of ``outputting run-length codes in the order in which they occur'' in order to make codes decodable. In the example in Figure 11, when K=1, e _i =0 and M _i =1, first
A run for M _i =1 occurs, and when k=2, e _i =
0, M _i =1, this run continues, and when k = 3, e _i
When k=0, M _i =0, a run for M _i =0 occurs for the first time, when k=4, e _i =0, and M _i =0, this run continues, and when k=5, e _i =1, M _i =0 and M _i =0
The run for is completed with run length 2 and code C2 is generated. That is, at the time of k=5, M _i =1
The run for M _i =
Although this occurs earlier than the run for 0, a run length code for it has not yet been generated. on the other hand
The run for M _i =0 occurred later than the run for M _i =1, but ended with length 2 at k=5, so run length code C2 was generated earlier. Therefore, if C2 is output as RLCD immediately after the generation ends, that code will be output before the run for M _i =0 that occurred earlier, resulting in a code sequence that cannot be decoded. In order to avoid this, the switch signal generation circuit 41 operates so that if the mode signal M _i =1 in the initial state where the counters 83 and 87 are cleared and COU0 = 0 and COU1 = 0, then the switch signal generating circuit 41 performs a run prior to the run of M _i =0. detects that a run for M _i =1 has occurred, sets SWCH to H level, and connects the switch circuit 42 to connect RLC1 to the selection circuit 46 and RLC0 to the memory 43,
RLC0 is first written to the memory 43. Conversely, if M _i =0 in the initial state, it is detected that a run for M _i =0 occurs before a run for M _i =1, and SWCH is set to L.
Set the switch circuit 42 to RLC0 level.
is connected to the selection circuit 46 and RLC1 is connected to the memory 43, so that RLC1 is written to the memory 43 first. Again, follow the specific signal changes in the time chart. At k=5, RLC0=C2 was generated and written to the memory 43, but in the same way, RLC0=C2 was generated and written to memory 43.
=7,9, the end of the run of length 1 and length 0 for M _i =0 is detected, and the corresponding run length codes RLC0 =C3, C4 are written in the memory 43. Between k=1 and 9, e _i for M _i =1 is all 0, and M _i = 1 occurred when k=1.
The run for 1 continues without ending. k=
10, e _i = 1, M _i = 1, and the end of the run for M _i = 1 is detected for the first time, and the counter 83 is detected by RCS1 generated from the run end detection circuit 86.
The content COU1=3 is the run length code generator 84
Immediately thereafter, the counter 83 is reset. Further, RCS1 sets the input inhibit circuit 57, sets IHB1 to H level, sets INHB to H level, and registers 38 and 39 output prediction error signals e ₁ , e ₂ ,
Temporarily prohibits input of e ₃ and mode signals M ₁ , M ₂ , and M ₃ . The run length code generator 84 is
Run length code RLC1= corresponding to COU1=3
Since SWCH is H, RLC1 is connected to the selection circuit 46 via the switch circuit 42.
Since REDM is L, the selection circuit 46 selects this,
It is output as the output code RLCD of this encoding circuit.
Code C1 corresponding to M _i =1 was generated after codes C1, C2, and C3 corresponding to M _i =0, but the run for code C1 started to be generated when k=1, and code C2 , C3, and C4. Therefore, based on the principle of "outputting run-length codes in the order of run occurrence," code C1 was first output as RLCD. After the run-length code generation circuit 84 finishes generating the code C1,
Since SWCH is at H level, the selection circuit 40 selects RCE1 and outputs it as RLCE. RLCE sets flip-flop 44
REDM is set to H level, and selection circuit 46 receives REDM at H level, selects memory 43, reads out the contents C2, C3, and C4, and outputs them as output code RLCD of the present encoding circuit. While REDM is at H level, INHB is at H level, and e ₁ , e ₂ , e ₃ , M ₁ ,
Input of M ₂ and M ₃ is temporarily prohibited. When all the contents of the memory 43 are read out and become empty, the memory 43 is
MEMP is generated and MEMP is flip-flop 4
4 is reset, REDM is set to L level, and reading from the memory 43 is stopped. When REDM goes to L level, INHB goes to L level and e ₁ , e ₂ , e ₃ ,
Input of M ₁ , M ₂ , and M ₃ is resumed. The switch signal generation circuit 41 inputs MEMP as a trigger signal, and as shown in Table 18, COU1,
Outputs a new SWCH signal based on COU0 and M _i .
Let me explain Table 18 in detail. When MEMP occurs, the SWCH signal changes, but the timing is first to output RLC1 directly as RLCD without going through the memory 43, and then to output the signal in the memory 43.
Immediately after reading RLC0 and outputting it as RLCD, and secondly, after outputting RLC0 directly as RLCD without going through the memory 43,
This is right after reading RLC1 and outputting it as RLCD. In the first case, counter 83 is cleared by RCS1.

[Table] When COU1=0 and the second time, counter 87
is cleared by RCS0 and COU0=0,
In any case, when MEMP occurs, COU1 and COU0
Either one is 0. COU1=COU0=0
At this time, there is no run being counted by the counters 83 and 87, so the run length code to be output as RLCD is first determined based on M _i . That is, M _i
If = 0, set SWCH to L level and RLC0 first, if M _i = 1, set SWCH to H level and RLC1
The switch circuit 42 is set to output first. The deferred run-length code is stored in memory 4.
Once written to 3, the code to be output first is
After being output as an RLCD, it is read out and output as an RLCD. COU1=0, COU0≠
When it is 0, the counter 87 is counting runs for M _i =0, so it is necessary to first output the code corresponding to the run being counted as RLCD.
Therefore, the switch circuit 42 is set to set SWCH to L level and output RLC0 first. RLC1
is once written to the memory 43, and after RLC0 is output as RLCD without going through the memory, the memory 4
3 and output as RLCD. When COU1≠0 and COU0=0, the counter 83 is counting runs for M _i =1, so first the code corresponding to the run being counted is RLCD.
It needs to be output as . Therefore, the switch circuit 42 is set to set SWCH to H level and output RLC1 first. RLC0 is once memory 43
, RLC1 is output as RLCD without going through memory, and then read from memory 43.
It will be output as RLCD. This is the 18th
This is an explanation of the table. MEMP occurs at k=11, but COU0=
Since COU1 = 0, M _i = 0, SWCH according to Table 18
becomes L level. Since e _i =1 at k=11,
The run for M _i =0 ends at the same time as the run length is 0, run length code C5 is generated as RLC0, and SWCH is at L level, so the run is passed through the switch circuit 42 and the selection circuit 46 without going through the memory 43.
Output as RLCD. Run length code C5
When the output of the run-length code generator 88 is completed,
generates RCE0, and the selection circuit 40 receives RCE0.
Since SWCH is at L level, it is output as RLCE. Flip-flop 44 is set by RLCE and outputs REDM at H level. The selection circuit 46 receives the H level REDM and selects the memory 43 and attempts to read its contents, but since nothing is written in the memory 43, MEMP is immediately output. The flip-flop 44 is set by MEPM and REDM goes to L level. Selection circuit 4
6 stops reading from the memory 43 upon receiving the L level REDM, and selects the output of the switch circuit 42. Registers 38 and 39 are set when REDM goes low.
Since INHB becomes L, e ₁ , e ₂ , e ₃ , M ₁ , M ₂ , M ₃
Resume input. In the end, it is only a moment that REDM reaches H level, and there is no particular note on the time chart. k=
12, the switch signal generation circuit 41 is
Upon receiving MEMP, it outputs an H level SWCH based on COU1=COU0=0 and M _i =1 (see Table 18). Since e _i = 1 at k = 12, the run for M _i = 1 ends with a run length of 0 as soon as it occurs, and RLC1
Run length code C6 is generated as SWCH
Since it is at H level, it is output as RLCD through the switch circuit 42 and the selection circuit 46 without going through the memory 43. When the output of the run-length code C6 is completed, the run-length code generator 84 generates RCE1, and the selection circuit 40 receives RCE1 and outputs it as RLCE since SWCH is at H level. Flip-flop 44 is set by RLCE and outputs REDM at H level. The selection circuit 46 receives the H level REDM and attempts to read the memory 43, but since nothing is written in the memory 43, MEMP is immediately output.
The flip-flop 44 is reset by MEMP and REDM becomes L level. The selection circuit 46 receives the L level REDM, stops reading from the memory 43, and selects the output of the switch circuit 42.
Registers 38 and 39 are set when REDM goes low.
Since INHB becomes L, e ₁ , e ₂ , e ₃ , M ₁ , M ₂ ,
Resume inputting _M3 . After all, REDM reaches H level in an instant, and there is no particular note on the time chart. At k=13, the switch signal generation circuit 41 receives MEMP, and COU1=COU0=
0, M _i =1 (see Table 18)
Output SWCH. For k=13, 14, 15, e _i
= 0, so no run-length code is generated, but k
= 16, e _i = 1, M _i = 0, COU0 = 1, so
Run length code C with run length 1 for M _i =0
8 is generated as RLC0, and since SWCH is at H level, RLC0 is temporarily written into the memory 43 via the switch circuit 42. When the generation of the run-length code C8 is finished, the run-length encoder 88
RCE0 is generated, and the selection circuit 40 receives RCE0, but since SWCH is at L level, it is not selected.
RLCE is not output. For k=17, e _i =0
Therefore, no run-length code is generated, but k = 18
In, e _i = 1, M _i = 1, COU1 = 2, so M _i =
The run length code C7 with run length 2 for 1 is
It is generated as RLC1 and SWCH is at H level.
RLC1 is the switch circuit 42 without going through the memory 43,
It passes through the selection circuit 46 and is output as RLCD.
When the output of the run-length code C7 is completed, the run-length code generator 84 generates RCE1, and the selection circuit 40 receives RCE1 and outputs it as RLCE since SWCH is at H level. flipflop 4
4 is set by RLCE and outputs H level REDM. The selection circuit 46 receives the H level REDM, selects the memory 43, reads out its contents C8, and outputs it as the output code RLCD of the main encoding circuit.
When all the contents of the memory 43 are read out and become empty, the memory 43 generates MEMP, which resets the flip-flop 44, sets REDM to L level, and stops reading the memory 43. At k=19, the switch signal generation circuit 41 receives MEMP,
Based on COU1=0, COU0=1 (see Table 18)
Outputs L level SWCH. This is because the run length counter 87 is currently counting the run for M _i =0 that occurred at k=17, so the code corresponding to the run that is being counted is first outputted as the RLCD. For k=19, 20, 21, e _i =0, M _i
Since =1, no run length code is generated and the counter 83 is counted up. At k=21
The time chart in Figure 11 ends with e _i = 0, M _i = 1, COU1 = 2, and COU0 = 1, but
The counters 83, 87 are then counting the run length for both M _i =0 and M _i =1, and the actual operation continues, but is not shown in FIG. This concludes the description of the encoding device of the present invention. Next, let me supplement the explanation of the decoding device that is paired with this. FIG. 12 shows a block diagram of a decoding device that is paired with the encoding device of the present invention. In FIG. 12, the decompression decoding circuit 18 outputs the prediction error encoded signal
is input and decompressed and output as a prediction error signal 47, and the prediction decoding circuit 19 outputs the prediction error signal 47.
7 and performs predictive decoding to generate a decoded image signal 48
Output as . It is assumed that the prediction error encoded signal 45 is generated by the encoding device of the present invention which has already been described in detail. The control circuit 20 sends out clock signals, control signals, and synchronization signals to control each circuit. FIG. 13 is a block diagram showing an embodiment of the predictive decoding circuit 19 for a color image signal of eight colors (0 to 7) (3 bits per pixel). To simplify the explanation, in this example, it is assumed that the image signal S used for prediction consists of the four pixels a, b, c, and d shown in FIG. Also, each pixel is represented by 3 bits, and each color is represented by the first
As shown in the table (0, 0, 0), (0, 0, 1),...
Suppose that it corresponds to (1, 1, 1). Of course, by expanding this example, it is easy to construct a circuit for S consisting of a large number of pixels and a color image signal having an even larger number of levels. In the predictive decoding circuit 19, as shown in FIG. 13, there are already 3 (l+2) decoded image signals.
It is set in the bit shift register 28. Here, l represents the number of pixels per main scanning line. The first mode signal determination ROM 23 includes a, b,
4 pixels c and d (3 bits for each pixel) are input as address data, and based on that, the mode signal M ₁ (1
bits). Mode signal M ₁ is selected by selection circuit 27 and sent to prediction error signal decoding circuit 18 as mode signal M _i . The decompression decoding circuit 18 receives _M1 and generates a prediction error signal corresponding to _M1.
e ₁ is decompressed and decoded and added to the predictive decoding circuit 19.
The expansion decoding circuit 18 expands and decodes the prediction error signal e _i 47 corresponding to the input mode signal M _i from the compressed code, and applies it to the prediction decoding circuit 19 . In the prediction decoding circuit 19, the prediction error signal e _i 47 is sent to the second mode signal generation ROM 24 together with the already decoded reference image signals a, b, c, d (3 bits each).
Added as hair address data. ROM24
is the second mode signal based on this address data.
_M2 is generated and applied to the selection circuit 27. Selection circuit 2
7 selects M ₂ and sends it to the expansion decoding circuit 18 as a mode signal M _i . The decompression decoding circuit 18 receives M ₂ and uses the prediction error signal e ₂ corresponding to M ₂ as e _i to generate the prediction decoding circuit 19.
Add to. In the prediction decoding circuit 19, the prediction error signal e ₂ 47 is added to the ROM 25, and until now the ROM
The prediction error signal e ₁ corresponding to the mode signal M ₁ applied to the 1-bit register 21 is set to the 1-bit register 21 . The prediction error signals e ₁ and e ₂ corresponding to M ₁ and M ₂ are added as address data to the third mode signal generation ROM 25 together with the already decoded image signals a, b, c, and d. The ROM 25 generates a third mode signal M ₃ based on this address data and applies it to the selection circuit 27 . The selection circuit 27 selects M ₃ and sends it to the expansion decoding circuit 18 as a mode signal M _i . The expansion decoding circuit 18 receives M ₃ and adds a prediction error signal e ₃ corresponding to M ₃ to the prediction decoding circuit 19 as e _i . In the prediction decoding circuit 19, the prediction error signal _e3 47 is applied to the color signal selection circuit 50 as a control signal, and the prediction error signal _e2 corresponding to the mode signal _M2 , which has been applied to the ROM 25, is set to the register 21. The prediction error signal e ₁ corresponding to the mode signal M ₁ which was set in the register 21
is set in register 22. The contents e ₁ and e ₂ of the registers 21 and 22 are applied as control signals to the level signal selection circuit 50 similarly to e ₃ . In the end, the prediction error signals e ₁ , e ₂ , e ₃ corresponding to the mode signals M ₁ , M ₂ , M ₃ are sent to the color signal selection circuit 50 as a control signal e.
= (e ₁ , e ₂ , e ₃ ). Ranking determination
The ROM 26 stores decoded image signals a, b, c, d.
is input as address data, and eight ranked color signals α ₁ , α ₂ , . . . , α ₈ (3 bits each) are outputted and added to the level signal selection circuit 50 as input data. The color signal selection circuit 50 has α ₁ , α ₂ ...,
α _i that has a subscript i that matches the number e+1 obtained by adding 1 to the control signal e (3 bits) from among α ₈ , that is, α _e+1
is selected and set in the register 28 as the decoded image signal x. Here, e is e ₁ MSB and e ₃ is LSB
I thought of it as a binary number. When the register 28 receives x, it shifts the stored data by one pixel and prepares for the decoding operation of the next pixel. Predictive decoding circuit 1
ROM 2 for generating 1st, 2nd, and 3rd mode signals of 9
3, 24, 25, the ranking determination ROM 26 is for generating the first, second, and third mode signals of the predictive encoding circuit 2.
The ROMs 15, 16, 17 and ranking determining ROM 9 are exactly the same. FIG. 14 is a block diagram showing one embodiment of the decompression/decoding circuit 18. Prediction error decoding circuit 18
As shown in the figure, it is roughly divided into two parts, upper and lower. The upper part is a decoding circuit for the prediction error encoded signal corresponding to M _i =1, and the lower part is a decoding circuit for the prediction error encoded signal corresponding to M _{i =1} .
This is a decoding circuit for a prediction error encoded signal corresponding to =0. The role of the decompression decoding circuit 18 is to receive the mode signal M _i from the predictive decoding circuit 19 and output the corresponding prediction error signal e _i to the predictive decoding circuit 19. When it receives a mode signal where M _i =0, The upper circuit operates, and upon receiving a mode signal of M _i =1, the lower circuit operates. The buffer memory 29 contains a prediction error encoded signal.
The RCLD 45 is run-length encoded and stored, and when M _i =1, it is read out by the run-length decoding circuit 31 upon request.
When M _i =0, the run length decoding circuit 23
It will be read when there is a further request. The run-length decoding circuit 31 is a circuit that decodes the prediction error coded signal RLC1 for M _i =1, and receives the decoding start signal RDS1 from the decoding start signal generation circuit 33 and starts its operation. When the run length decoding circuit 31 starts operating, the switch circuit 30
The prediction error coded signal RLC1 is read out from the buffer memory 29 via the buffer memory 29, the run length obtained by decoding is set in the counter 35, and a decoding end signal RDE1 is output. The counter 35 counts down when the countdown enable signal ENB1 is H, and when the content CON1 becomes 0, the output of the prediction error signal generation circuit 37 is set to H level ('1'). Counter 35 further counts down and contents CON1
When becomes -1, the decoding start signal generation circuit 33
generates a pulse signal RDS1 to start the operation of the run-length decoding circuit again. The flip-flop 67 outputs the decoding start signal RDS1 to the OR circuit 65.
is set by inputting through the decoding end signal
It is reset by inputting RDE1 through the OR circuit 66. At this time, the output of flip-flop 67
DECD indicates that the run length decoding circuit 31 is in decoding operation. The delay circuit 68 is
Outputs the DECD signal with a 1 clock delay. The output of the delay circuit 68 is inverted by the NOT circuit 68 and becomes a countdown enable signal.
ENB and add to AND circuits 61 and 62. ENB,
When M _i is at H level ('1'), ENB1 becomes H level and counter 35 counts down. ENB
is at H level When M _i is at L level ('0'), ENB0 goes to H level and the counter 36 counts down. The prediction error coded signal RLC0 for the circuit M _i =0 in the lower part of FIG. 14 is decoded. and,
Signals RDS0, RDE0, CON0, ENB0, run length decoding circuit 32, counter 36, decoding start signal generation circuit 34, prediction error signal generation circuit 60
is the signal RDS1, in the circuit for M _i =1,
It functions similarly to RDE1, CON1, ENB1, run length decoding circuit 31, counter 35, decoding start signal generation circuit 33, and prediction error signal generation circuit 37. 14 according to the time chart in Figure 15 below.
The operation of the prediction error decoding circuit 19 shown in the figure will be explained.
In FIG. 15, k written at the top indicates the order in which the mode signal M _i written below is input. The prediction error signal e _i corresponding to the mode signal M _i is sometimes output immediately after inputting M _i , such as when k = 2, 4, 5, etc., but when k = 1, 3, 6, etc. In some cases, the output is output after waiting for a while. The x mark in the e _i column indicates the e _i output waiting time, during which the run length decoder 31 or 32 operates and the run length code of e _i corresponding to the input M _i is decoded. When e _i is output without waiting time, the run-length code corresponding to e _i has already been decoded. Prediction error decoding circuit 1
9 starts the operation when k=1. At the start of the operation, ENB is at the H level and DECD is at the L level. The contents CON1 and CON0 of the counters 35 and 36 are initialized to 0. At the start of operation, ENB
Since M _i =1, ENB1 becomes H level and the counter 35 counts down.
When M _i =0, ENB0 becomes H level and the counter 36 counts down. In Figure 15, k=
When M _i =1, the counter 35 counts down and its content CON1 becomes -1. Since CON1 is -1, the decoding start signal generation circuit 33 outputs a signal.
RDS1 is generated to start the operation of the run length decoding circuit 31. Further, RDS1 sets the flip-flop 67 via the OR circuit 65 and sets the signal DECD to H level. The run-length decoding circuit 31 starts operating, inputs the run-length code C1 as RLC1 from the buffer memory via the switch circuit 30, and decodes it. When the run-length decoding circuit 31 finishes decoding the run-length code C1, it sets the result in the counter 35 and issues a signal RDE1 to the OR circuit 6.
6, the flip-flop 68 is reset and the signal DECD is set to L level, thereby notifying the completion of decoding. The prediction error signal generation circuit 37 outputs a signal when the decoding result '3' of C1 is set in the counter 35.
A received signal e _i (1)=0 is generated as CON1, and this is outputted via the selection circuit 64 as a prediction error signal e _i . While the run-length decoding circuit 31 is operating, the DECD signal is at H level. Since the ENB signal is at the L level one clock later, the decoding result is set in the counter 35 one clock after the run-length decoding circuit 31 starts operating, and e _i is output based on it. In other words, until the next mode signal M _i is input, the counter 35
countdown is prohibited. Note that the clock signal is indicated as CLK at the bottom of FIG. 15, and this decompression/decoding circuit operates in synchronization with CLK.
This concludes the explanation when k=1, and then begins the explanation when k=2. In Fig. 15, when k=2, M _i
=1, since ENB is at H level, ENB1 is at H level, the counter 35 counts down, and its content CON1 becomes 2. Since CON1 is 2, the prediction error signal generation circuit 37 generates a signal e ₁ (1)=0 and outputs this via the selection circuit 64 as the prediction error signal e _i . When k=1, the run length decoding circuit 31 is operating after inputting the mode signal M _i (3 in FIG. 15).
(during the clock) There was some time waiting for the output of e _i , but
When k=2, the prediction error signal e _i can be generated immediately from the value already set in the counter 35 without operating the run-length decoding circuit 31 or 32, and there is no need for waiting time. This concludes the explanation for k=2, and then begins the explanation for k=3. When k=3, M _i =0 and ENB is at H level, so
ENC2 is at H level, the counter 36 counts down and its content CON0 becomes -1.
Since CON0 is -1, decoding start signal generation circuit 3
4 issues the signal RDS0 and starts the operation of the run length decoding circuit 32. Also, RDS0 is OR
The flip-flop 67 is set via the circuit 65, and the signal DECD is set to H level. The run length decoding circuit 32 starts operating and the switch circuit 30
Run-length code C from buffer memory via
2 as RLC0 and decode it. When the run-length decoding circuit 32 finishes decoding the run-length code C2, it sets the result in the counter 36, generates the signal RDE0, resets the flip-flop 68 via the OR circuit 66, and sets the signal DECD to L level to notify the end of the decoding. Prediction error signal generation circuit 6
0 receives the decoding result '2' of C2 set in the counter 36 as the signal CON0 and sends the signal e _i (0).
=0 and outputs it via the selection circuit 64 as the prediction error signal e _i . While the run-length decoding circuit 32 is operating, the DECD signal is at H level. Since the ENB signal is at the L level one clock later, the decoding result is set in the counter 36 one clock after the run-length decoding circuit 32 starts operating, and the decoding result is set in the counter 36 based on it until e _i is output. The countdown of the counter 35 is prohibited until the mode signal M _i is input.
This concludes the explanation when k=3. k=4～
The same operation continues for 21, and run length codes C3 to C10 are decoded and each mode signal is
A prediction error signal e _i corresponding to M _i is generated. In the color image signal encoding device of the present invention, the operation of the compression encoding circuit 4 shown in FIG. 10 will be explained with reference to the time chart shown in FIG. That's what I said. The operation of the decompression decoding circuit 18 in FIG. 14 has been explained using the time chart in FIG. 15. At that time, the run-length codes C1, C2, .
They are exactly the same as C1, C2, . . . , C8 in the figure. As a result, C1, C2,... shown in FIG.
..., C8 decoding result e _i is shown in FIG _.
This shows that the decompression/decoding circuit 18 is operating correctly. This concludes the explanation of the decompression decoding circuit 18, and also the explanation of the color image signal decoding device that is paired with the encoding device of the present invention. Although we have explained the case where both the encoding device and the decoding device are 8-level image signals, N(2 ^n-1
It is easy to extend this to the case of image signals with values <N2 ⁿ ). In the case of N (2 ^n-1 < N2 ⁿ ), the prediction error signal e consists of n bits e ₁ , e ₂ , ..., e _o (1 bit each), and depends on the connection method of e _i and the run. The definition is the same as for 8 values. As described above in detail, according to the encoding device of the present invention, color image signals can be efficiently encoded and decoded using a run-length encoder.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the encoding device of the present invention, FIG. 2 is a diagram showing the positional relationship between a reference pixel and a predicted pixel, and FIG. 3 is a diagram of a predictive encoding circuit used in the encoding device of the present invention. Block diagram showing the embodiment, No. 4
Figures 5, 6, and 7 are diagrams showing examples of conditional occurrence probabilities of image signals; Figures 8 and 9 are diagrams explaining the coding order of prediction error signals; The figure is a block diagram showing an example of the prediction error encoding circuit of the encoding device of the present invention, FIG. 11 is a time chart of the prediction error encoding circuit of FIG. 10, and FIG. 12 is a block diagram of the prediction error encoding circuit of the encoding device of the present invention. FIG. 13 is a block diagram showing an embodiment of the predictive decoding circuit used in the decoding device of the present invention, and FIG. 14 is a block diagram showing an embodiment of the prediction error decoding circuit of the decoding device of the present invention. The block diagram shown in FIG. 15 is a time chart of the prediction error decoding circuit shown in FIG. In the figure, 1,48...color image signal, 2...
...Prediction encoding circuit, 3,47...Prediction error signal,
4... Compression encoding circuit, 5, 45... Encoded prediction error signal, 6, 20... Control circuit, 7, 28...
3(l+2) bit shift register, 8, 26...
...ROM for ranking determination, 9...ranking signal selection circuit,
15, 23...ROM for determining the first mode signal, 1
6, 24...ROM for determining second mode signal, 1
7, 25... ROM for determining third mode signal, 18
... decompression decoding circuit, 19... predictive decoding circuit,
21, 22...1 bit register, 27, 40,
46, 76, 77... selection circuit, 31, 32...
Run length decoding circuit, 29... Buffer memory, 35, 36, 83, 87... Counter, 3
3, 34... Run length decoding circuit start signal generator, 30, 42... Switch circuit, 37,
60...Prediction error signal generation circuit, 38, 39,...
...3-bit register, 41...Switch signal generation circuit, 43...Run length code memory, 44,
57, 58, 67...flipflop, 50...
...Color signal selection circuit, 52, 65, 66...OR circuit, 61, 62, 81, 82, 93, 94...
AND circuit, 63, 69, 78, 79, 80...
NOT circuit, 68...Delay circuit, 86, 90
. . . Run end detection circuit, 84, 88 . . . Run length code generator.

Claims (1)

[Claims] 1. Means for arranging N signal values for predicting the next input image signal x based on the already input color image signal S of N (2 ^n-1 <N2 ⁿ ) colors in order of prediction accuracy; means for detecting the order in which the actual signal value of the signal x coincides with the arranged signal values, and generating at most n prediction error signals e _i (1in) corresponding to the order; means for predictively encoding the image signal x; and a mode signal M _i indicating a high probability that each prediction error signal e _i (1in) is 0; when i=1, only the color image signal S; Occurs based on 2in
When , means for generating based on the color image signal S and i-1 prediction error signals e _j (1j1-1), and each prediction error signal e _i (1in)
and each mode signal M _i (iin) corresponding to it
1. A color image signal encoding device comprising means for compression encoding after grouping based on.