JPS6327063A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6327063A
JPS6327063A JP61170023A JP17002386A JPS6327063A JP S6327063 A JPS6327063 A JP S6327063A JP 61170023 A JP61170023 A JP 61170023A JP 17002386 A JP17002386 A JP 17002386A JP S6327063 A JPS6327063 A JP S6327063A
Authority
JP
Japan
Prior art keywords
layer
oxygen
substrate
ions
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61170023A
Other languages
Japanese (ja)
Other versions
JPH0734478B2 (en
Inventor
Bunji Mizuno
文二 水野
Masabumi Kubota
正文 久保田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61170023A priority Critical patent/JPH0734478B2/en
Priority to US07/073,829 priority patent/US4837172A/en
Publication of JPS6327063A publication Critical patent/JPS6327063A/en
Publication of JPH0734478B2 publication Critical patent/JPH0734478B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

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  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a surface silicon layer having no oxide precipitate by outward diffusing remaining unnecessary impurity to be implanted due to ion implantation at the time of manufacturing an SOI structure by implanting light element ions. CONSTITUTION:An oxygen ion beam 4 is emitted to the surface of a silicon substrate 2, and a buried oxygen layer 6 is formed in the substrate. In this case, a layer 10 which contains a large quantity of oxygen upon damaging of emitting is formed between the layer 8 remaining on the surface and the layer 6, and the oxygen remains also on the layer 8. In order to remove the remaining unnecessary introduced oxygen, a hydrogen ion beam 12 is implanted as light element ions in the state that the substrate is held at high temperature. Thus, a surface silicon layer 14 having low oxygen density is obtained. An MOS transistor 16 is formed in the layer 14 on the surface of the thus processed substrate.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はイオン注入による半導体装置の製造方法に関す
るものであシ、特にシリコン層と組成比の正しい絶縁物
層が急峻な界面で接する５ＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ
　Ｉｎ５ｕｌａｔｏｒ）基板からなる半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device by ion implantation, and particularly relates to a method of manufacturing a semiconductor device by ion implantation, and particularly to a method for manufacturing a semiconductor device using ion implantation.
The present invention relates to a method of manufacturing a semiconductor device including an In5ulator substrate.

従来の技術 （ト）例えば酸素イオンを注入してＳＯＩ構造を作り、
この構造に半導体素子を作り込むＳＩＭＯＸ技術（Ｓｅ
ｐａｒａｔｉｏｎ　ｂｙ　ＩＭｐｌａｎｔｓｃｌ、　Ｏ
Ｘｙｇｅｎ）の場合について第３図、第４図を用いて説
明する。Conventional technology (g) For example, by implanting oxygen ions to create an SOI structure,
SIMOX technology (Se
paration by IMplantscl, O
The case of Xygen) will be explained using FIGS. 3 and 4.

シリコン単結晶２の（１ｏｏ）面２Ａに１６０＋ヒーム
４を８’０ＫｅＶの加速エネルギーで１×１０１８ｉｏ
ｎｓ／ｄ注入し、窒素雰囲気中１１５０℃で熱処理して
絶縁物層６を形成する。２Ｂは単結晶２の上層に残され
た部分である。しかるのち、第３図すの様に１μｍ程度
のエピタキシャル層２８を積み、この層２８に第３図Ｃ
の様に所定の半導体素子１６を形成している（Ｙ、Ｑｎ
ｕｃｒａ　ｅｔ　ａｌ、ＶＬｓＩＳｙｍｐｏｓｉｕｍ　
（ブイ　エルニスアイ　シンポジウム）Ｋｏｂｅ　（１
９８６）２４−２５）。１８は領域２Ｂ。160 + beam 4 on (1oo) plane 2A of silicon single crystal 2 at 1×1018io with acceleration energy of 8'0 KeV
The insulator layer 6 is formed by ns/d implantation and heat treatment at 1150° C. in a nitrogen atmosphere. 2B is a portion left in the upper layer of the single crystal 2. After that, an epitaxial layer 28 of about 1 μm is deposited as shown in FIG.
A predetermined semiconductor element 16 is formed as shown in (Y, Qn
ucra et al, VLsISymposium
(Bui Ernis Eye Symposium) Kobe (1
986) 24-25). 18 is area 2B.

２８の一部が酸化された周辺絶縁物領域２６はゲート電
極、２０．２２はソース、ドレイン電極、２４はゲート
絶縁物である。この様な方法で形成されたＳＯＩ基板は
、実際第３図すにおいて、表面エピタキシャル層２８を
除くと第３図の様に表面側からシリコン単結晶層８、照
射損傷を受は酸イーで２．２５　Ｘ　１０１８ｉ　ｏｎ
ｅ　／ｄ注入し窒素雰凹気中１２６０℃以上の熱処理を
施す事によって表面側のシリコン単結晶層中の不純物酸
素が殆んで無くなり、急峻な界面を得る事が、（ＢＹ　
Ｍａｏ　ａｔ　ａｌ。A peripheral insulating region 26 in which a portion of 28 is oxidized is a gate electrode, 20.22 is a source and drain electrode, and 24 is a gate insulator. In fact, in the SOI substrate formed by this method, as shown in FIG. 3, except for the surface epitaxial layer 28, the silicon single crystal layer 8 is exposed to radiation damage from the surface side as shown in FIG. .25 x 1018i on
By performing e/d implantation and heat treatment at 1260°C or higher in a nitrogen atmosphere, the impurity oxygen in the silicon single crystal layer on the surface side is almost eliminated and a steep interface is obtained.
Mao at al.

Ａｐｐｌ、Ｐｈｙｓ、Ｌｅｔｔ、（アプライ　フィジッ
クス　レター）４８（１２）、２４Ｍａｒｃｈ（１９８
６）７９４）に示されている。Appl, Phys, Lett, (Apply Physics Letter) 48 (12), 24 March (198
6)794).

発明が解決しようとする問題点 従来の方法（ハ）ではイオン注入に際して起こる照射損
傷の為、表面側のシリコン単結晶層２８とＳ　１０２層
６との間に第３図に示す如く広く損傷層１０が残り、こ
の層１ｏが５ｉ−８ｉＯ２界面の急峻性を低下させ、又
表面シリコン単結晶層２８に半導体素子を形成した場合
リーク電流の経路となる。Problems to be Solved by the Invention In the conventional method (c), due to irradiation damage that occurs during ion implantation, a damaged layer is formed widely between the silicon single crystal layer 28 on the surface side and the S102 layer 6 as shown in FIG. 10 remains, and this layer 1o reduces the steepness of the 5i-8iO2 interface, and also becomes a path for leakage current when a semiconductor element is formed on the surface silicon single crystal layer 28.

又表面シリコン層２８中に残留する酸素不純物が引き続
く製造プロセスに於いてドナーとなりＭＯＳトランジス
タの閾電圧を変動させる等の影響を及ぼす（ＤＡＶＩＤ
　　Ｊ、ＦＯ５ＴＥＲｅｔａｌ、ＩＥＥＥ　Ｔｒａｎｓ
。In addition, oxygen impurities remaining in the surface silicon layer 28 become donors in the subsequent manufacturing process and have an effect such as changing the threshold voltage of the MOS transistor (DAVID).
J,FO5TERetal,IEEE Trans.
.

Ｅｌｅ、Ｄｅｖ、（アイイイイ　トランザクション　エ
レクトロン　　デバイス）ＶＯＩ　ＥＤ３３（３）（１
９８６）　３５４　）。Ele, Dev, (Iii Transaction Electron Device) VOI ED33 (3) (1
986) 354).

従来の方法（至）では１２６０℃以上という半導体プロ
セスに於いては異常な高温処理を必要とする為、熱処理
炉材料からの重金属汚染が問題となる。Conventional methods require processing at temperatures above 1260° C., which is unusually high for semiconductor processes, and heavy metal contamination from heat treatment furnace materials becomes a problem.

問題点を解決するための手段 本発明の方法は、イオン注入によるＳＯＩ基板作製時に
、先ず絶縁物層を形成するに足る量の第１のイオンを注
入し、続いて基板を所定の温度に設定して、所定の飛程
で軽元素の第２のイオンを注入した後熱処理を施し、Ｓ
ＯＩ構造を形成して、表面側シリコン層に半導体素子を
作シ込むものである。Means for Solving the Problems The method of the present invention involves, when manufacturing an SOI substrate by ion implantation, first implanting first ions in an amount sufficient to form an insulating layer, and then setting the substrate at a predetermined temperature. After implanting second ions of a light element at a predetermined range, heat treatment is performed, and S
In this method, an OI structure is formed and a semiconductor element is fabricated in the silicon layer on the front side.

作　　用 ＳＯＩ構造基板作製時のイオン注入による表面側シリコ
ン層１４内の残留不要被注入不純物を、高温に於ける軽
元素イオンの注入による所謂Ｒａｄｉａｔｉｏｎ　ｅｕ
ｈａｎｃｅｄ　ｄｉｆｆｕｓｉｏｎ　により減少せしめ
、かつ不要不純物の存在による熱処理時の２次欠陥発生
をも減少せる事により、表面シリコン層と絶縁物層間の
損傷を軽減し、急峻な界面を得る。Function: Remaining unnecessary implanted impurities in the front side silicon layer 14 due to ion implantation during fabrication of the SOI structure substrate is removed by so-called Radiation Eu by implanting light element ions at high temperature.
By reducing hanced diffusion and also reducing the occurrence of secondary defects during heat treatment due to the presence of unnecessary impurities, damage between the surface silicon layer and the insulating layer is reduced and a steep interface is obtained.

実施例 以下にシリコン基板（１００）面に酸素イオンを注入し
た後、水素イーオンを注入した本発明の一実施例につい
て第１図を用いて説明する。シリコン基板２の（’１０
０　）表面２Ａに酸素イオンビーム４を例えば加速エネ
ルギー１８０　ＫｅＶで照射し、前記シリコン基板中に
埋め込み酸素物層６を形成する。この際には、イオン注
入の分布に従って表面に残るシリコン層８と酸化物層６
との間には照射損傷を伴う酸素を多量に含む層１０が形
成され、表面シリコン層８中にも固溶限度を越える濃度
の酸素が残留する。これら残留不要被注入酸素は引き続
く高温熱処理により析出物を形成したり、析出物形成に
伴う転位の発生を引き起こす。この様な析出もしくは転
位はＳＯＩ基板としては不純物の捕獲中心となったり、
キャリアの生成消滅中心となったりして、有害であり、
不要の酸素は除去する必要がある。EXAMPLE An example of the present invention in which hydrogen ions are implanted after oxygen ions are implanted into the surface of a silicon substrate (100) will be described below with reference to FIG. Silicon substrate 2 ('10
0) The surface 2A is irradiated with an oxygen ion beam 4 at, for example, an acceleration energy of 180 KeV to form an embedded oxygen layer 6 in the silicon substrate. At this time, the silicon layer 8 and oxide layer 6 remaining on the surface according to the distribution of ion implantation are
A layer 10 containing a large amount of oxygen, which is damaged by radiation, is formed between the silicon layer 8 and the surface silicon layer 8, and oxygen remains in the surface silicon layer 8 at a concentration exceeding the solid solubility limit. These residual unnecessary injected oxygen may form precipitates by subsequent high-temperature heat treatment, or cause dislocations to occur due to the formation of precipitates. Such precipitations or dislocations become the center of trapping impurities for SOI substrates,
It is harmful because it becomes the center of carrier generation and extinction.
Unnecessary oxygen needs to be removed.

そこで第１図ａに於ける基板を第１図すの様に３００℃
から１０００℃程度の高温、例えば６００℃に保ち、転
元素イオンとして水素イオンビーム１２を例えば加速エ
ネルギー１０ＫａＶで、ドーズ、は１ｏ１５〜１ｏ１８
ｉｏｎｓ殉例えば１０”ｔｏｎｓ／ｄ注入してやると、
酵素濃度の低い表面シリコン層１４を得る。すなわち、
層１０，８は酸素濃度の低い表面シリコン層１４となる
。この基板を１１００〜１２００′Ｃ例えば１１６０’
Ｃで熱処理した。Therefore, the substrate in Figure 1a was heated to 300°C as shown in Figure 1.
to 1000° C., for example, 600° C., and a hydrogen ion beam 12 is heated as a trans-element ion at an acceleration energy of 10 KaV, for example, at a dose of 1o15 to 1o18.
For example, if you inject 10” tons/d of ions,
A surface silicon layer 14 with a low enzyme concentration is obtained. That is,
Layers 10 and 8 become a surface silicon layer 14 with a low oxygen concentration. This board is heated to 1100-1200'C, for example 1160'
It was heat-treated at C.

第２図はそのシリコン基板中の酸素濃度をＳ　ＩＭＳ（
Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　５ｐｅｃｔｒ
ｏｓｃｏｐｙ）で測定したデータである。横軸は１次イ
オンＣｓ＋によるスパッタリングタイム、縦軸は２次イ
オン（酸素）のシグナル強度でいずれも任意単位である
。点線は単に１１５０℃で熱処理した従来の方法にもと
づく例で、表面シリコン部１４に酸素濃度のピーク９を
もつ、実線は本発明の実施例のものでピーク９は大幅に
減少し、表面シリコン層１４と埋め込み絶縁物層６の境
界にわずかにスパイク１１を残すのみである。この様に
処理したシリコン基板の表面シリコン層１４中に第１図
Ｃの様に例えばＭＯＳ）ランジスタ１６を形成する。１
８は周辺分離酸化物２０．２２はソース・ドレイン電極
、２４はゲート絶縁膜、２６はゲート電極である。Figure 2 shows the oxygen concentration in the silicon substrate measured by SIMS (
Secondary Ion Mass 5pectr
This is data measured using oscopy. The horizontal axis represents the sputtering time by the primary ions Cs+, and the vertical axis represents the signal intensity of the secondary ions (oxygen), both of which are in arbitrary units. The dotted line shows an example based on the conventional method of heat treatment at 1150° C., which has a peak 9 of oxygen concentration in the surface silicon layer 14, and the solid line shows an example of the present invention, in which peak 9 is significantly reduced, and the surface silicon layer 14 has a peak 9 of oxygen concentration. Only a small amount of the spike 11 remains at the boundary between the layer 14 and the buried insulating layer 6. For example, a MOS transistor 16 is formed in the surface silicon layer 14 of the silicon substrate thus treated, as shown in FIG. 1C. 1
8 is a peripheral isolation oxide 20, 22 is a source/drain electrode, 24 is a gate insulating film, and 26 is a gate electrode.

尚、軽元素イオンとして水素分子イオンもしくはヘリウ
ムイオンを用いても同様の結果が得られる。Note that similar results can be obtained by using hydrogen molecule ions or helium ions as the light element ions.

発明の効果 以上の様に本発明によれば、イオン注入によりＳＯＩ基
板を形成する際に、被注入イオンが本来とる分布に従っ
て表面シリコン層に残留する多量の不要酸素を軽元素イ
オン注入によるｒａｄｉｊ　ｔ　１ｏｎｅｕｈａｎｃｅ
ｄ　ｄｉｆｆｕｓｉｏｎにより外向拡散させる事が出来
、もって酸化析出物のない表面シリコン層と、埋め込み
絶縁物層が急峻な界面で接するＳＯＩ基板を得る。この
様にして形成されだＳＯＩ基板にＭＯＳ）ランジスタを
形成する際にはソース・ドレイン電極の拡散層を界面ま
で下げる事が出来、浮遊容量の低減というＳＯＩ構造本
来の特徴を生かした構造にする事が出来、高性能なＳ○
工型半導体装置作袈に寄与する。Effects of the Invention As described above, according to the present invention, when forming an SOI substrate by ion implantation, a large amount of unnecessary oxygen remaining in the surface silicon layer is removed by light element ion implantation according to the original distribution of the implanted ions. 1neuhance
D diffusion allows outward diffusion, thereby obtaining an SOI substrate in which a surface silicon layer free of oxidized precipitates and a buried insulating layer are in contact with each other at a steep interface. When forming a MOS (MOS) transistor on the SOI substrate formed in this way, the diffusion layer of the source/drain electrode can be lowered to the interface, creating a structure that takes advantage of the inherent feature of the SOI structure of reducing stray capacitance. A capable and high-performance S○
Contributes to the development of industrial semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の半導体装置の製造である。 ２・・・・・・シリコン基板、４・・・・・・酸素イオ
ンビーム、６・・・・・・埋め込み絶縁物層、８・・・
・・・酸素を含む表面シリコン層、１０・・・・・・損
傷層、１２・・・・・−水素イオンビーム、１４・・・
・・・表面シリコン層、１６・・・・・・半導体素子、
１８・・・・・・周辺絶縁物、２０・・・・・・ソース
電極、２２・・・・・・ドレイン電極、２４・・・・・
・ゲート酸化膜、２６・・・・・・ゲート電極。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第２
図 ＳＰＵＴＴＥＲＩＮＧ　Ｔ／ＭＥ　（’ａｒｂ、ｕｎｉ
ｔ）第３図 （ｂ’）FIG. 1 shows the manufacture of a semiconductor device according to an embodiment of the present invention. 2... Silicon substrate, 4... Oxygen ion beam, 6... Buried insulator layer, 8...
... Surface silicon layer containing oxygen, 10 ... Damaged layer, 12 ... - Hydrogen ion beam, 14 ...
...Surface silicon layer, 16...Semiconductor element,
18... Peripheral insulator, 20... Source electrode, 22... Drain electrode, 24...
・Gate oxide film, 26...Gate electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure SPUTTERING T/ME ('arb, uni
t) Figure 3 (b')

Claims (3)

【特許請求の範囲】[Claims] （１）シリコン単結晶基板内に第１のイオンの注入によ
って、埋め込み絶縁物層を形成した後、軽元素の第２の
イオンの注入によって前記絶縁物層上の前記基板の一部
よりなる表面シリコン層内に於ける残留不要被注入不純
物を外向拡散させ、前記表面シリコン層に半導体素子を
形成する事を特徴とする半導体装置の製造方法。(1) After forming a buried insulating layer in a silicon single crystal substrate by implanting a first ion, a surface formed of a part of the substrate on the insulating layer is formed by implanting a second ion of a light element. 1. A method for manufacturing a semiconductor device, comprising the steps of outwardly diffusing unnecessary implanted impurities remaining in a silicon layer to form a semiconductor element in the surface silicon layer. （２）第１のイオンの注入の被注入イオンとして酸素原
子を含むイオンもしくは窒素原子を含むイオンを用い、
軽元素の第２のイオンとして水素イオン、水素分子イオ
ンもしくはヘリウムイオンを用いる事を特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。(2) Using an ion containing an oxygen atom or an ion containing a nitrogen atom as an ion to be implanted in the first ion implantation,
2. The method of manufacturing a semiconductor device according to claim 1, wherein hydrogen ions, hydrogen molecule ions, or helium ions are used as the second ions of the light element. （３）軽元素を含むイオンの注入の際に被注入基板温度
を３００℃から１０００℃の範囲に上昇させる事を特徴
とする特許請求の範囲第１項又は第２項記載の半導体装
置の製造方法。(3) Manufacturing a semiconductor device according to claim 1 or 2, characterized in that the temperature of the implanted substrate is increased from 300°C to 1000°C during implantation of ions containing light elements. Method.
JP61170023A 1986-07-18 1986-07-18 Method for manufacturing semiconductor device Expired - Lifetime JPH0734478B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61170023A JPH0734478B2 (en) 1986-07-18 1986-07-18 Method for manufacturing semiconductor device
US07/073,829 US4837172A (en) 1986-07-18 1987-07-15 Method for removing impurities existing in semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61170023A JPH0734478B2 (en) 1986-07-18 1986-07-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6327063A true JPS6327063A (en) 1988-02-04
JPH0734478B2 JPH0734478B2 (en) 1995-04-12

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ID=15897167

Family Applications (1)

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JP61170023A Expired - Lifetime JPH0734478B2 (en) 1986-07-18 1986-07-18 Method for manufacturing semiconductor device

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Country Link
JP (1) JPH0734478B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144761A (en) * 1991-03-27 1993-06-11 Mitsubishi Materials Corp Method for manufacturing SOI substrate
FR2782572A1 (en) * 1998-04-17 2000-02-25 Nec Corp "SILICON-SUR-INSULATING" (SOI) SUBSTRATE AND MANUFACTURING METHOD THEREOF
US6316337B1 (en) 1997-09-24 2001-11-13 Nec Corporation Production process of SOI substrate
JP2002527907A (en) * 1998-10-15 2002-08-27 コミツサリア タ レネルジー アトミーク Method of manufacturing a material layer embedded in another material
JP2007281316A (en) * 2006-04-11 2007-10-25 Sumco Corp SIMOX wafer manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144761A (en) * 1991-03-27 1993-06-11 Mitsubishi Materials Corp Method for manufacturing SOI substrate
US5891265A (en) * 1991-03-27 1999-04-06 Mitsubishi Denki Kabushiki Kaisha SOI substrate having monocrystal silicon layer on insulating film
US6316337B1 (en) 1997-09-24 2001-11-13 Nec Corporation Production process of SOI substrate
FR2782572A1 (en) * 1998-04-17 2000-02-25 Nec Corp "SILICON-SUR-INSULATING" (SOI) SUBSTRATE AND MANUFACTURING METHOD THEREOF
FR2834821A1 (en) * 1998-04-17 2003-07-18 Nec Corp "SILICON-SUR-INSULATOR" (SOI) SUBSTRATE AND MANUFACTURING METHOD THEREOF
JP2002527907A (en) * 1998-10-15 2002-08-27 コミツサリア タ レネルジー アトミーク Method of manufacturing a material layer embedded in another material
JP2007281316A (en) * 2006-04-11 2007-10-25 Sumco Corp SIMOX wafer manufacturing method

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