JPS6331432U - - Google Patents
Info
- Publication number
- JPS6331432U JPS6331432U JP12553586U JP12553586U JPS6331432U JP S6331432 U JPS6331432 U JP S6331432U JP 12553586 U JP12553586 U JP 12553586U JP 12553586 U JP12553586 U JP 12553586U JP S6331432 U JPS6331432 U JP S6331432U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- operating means
- output lines
- input
- inputting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Power Sources (AREA)
- Input From Keyboards Or The Like (AREA)
Description
第１図はこの考案により構成された１つの好ま
しき実施例の要部抽出回路図、第２図は従来の典
型的な回路図である。
１１，１２……端子、１３，１４，１５……ゲ
ート、１６……トランジスタ、Ｌ１，Ｌ２，Ｌ３
，Ｌ４……入力ライン、Ｐ１，Ｐ２，Ｐ３，Ｐ４
……出力ライン。
FIG. 1 is a circuit diagram of a preferred embodiment constructed according to this invention, and FIG. 2 is a typical conventional circuit diagram. 11, 12... terminal, 13, 14, 15... gate, 16... transistor, L 1 , L 2 , L 3
, L 4 ... input line, P 1 , P 2 , P 3 , P 4
...Output line.
Claims (1)
ン上に構成される情報入力又は処理のための操作
手段と、上記操作手段において所定時間以上にわ
たつて操作がなされないとき該操作手段への給電
を中断する休止モードに対し、給電が回復する給
電モードへの切換を行う復帰手段とを有するキー
入力回路において、 上記復帰手段が接続されていないすべての入力
及び出力ラインを上記休止及び給電モードに応じ
て給電の制御を行う制御手段を備えていることを
特徴とするキー入力回路。[Claims for Utility Model Registration] An operating means for inputting or processing information configured on input and output lines formed in a matrix, and an operating means for inputting or processing information that is configured on input and output lines formed in a matrix, and when the operating means is not operated for a predetermined period of time or more. In a key input circuit having a return means that switches from a sleep mode in which power supply to the operating means is interrupted to a power supply mode in which power supply is restored, all input and output lines to which the above return means are not connected are A key input circuit characterized by comprising a control means for controlling power supply according to a pause and a power supply mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12553586U JPS6331432U (en) | 1986-08-19 | 1986-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12553586U JPS6331432U (en) | 1986-08-19 | 1986-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331432U true JPS6331432U (en) | 1988-03-01 |
Family
ID=31018514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12553586U Pending JPS6331432U (en) | 1986-08-19 | 1986-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331432U (en) |
-
1986
- 1986-08-19 JP JP12553586U patent/JPS6331432U/ja active Pending
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