JPS633228Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is a normally-on gallium arsenide field effect transistor (GaAs FET) that can operate stably over a wide range of speeds from low speeds to ultra-high speeds.
The present invention relates to a set-reset type flip-flop using.

In recent years, logic circuit ICs using GaAs FETs have attracted attention as logic circuit elements that operate at ultra-high clock rates exceeding 1 GHz and consume less power than conventional silicon bipolar transistors. There is. Among them, so-called normally-on GaAs FETs, in which the maximum drain current flows when the gate bias voltage is zero and the drain current decreases as a negative gate bias voltage is applied, have the advantage of being able to obtain a large gm and have a high logic amplitude. It is suitable for ultra-high-speed ICs because of its features such as large capacity and relatively easy manufacturing.

Figure 1 shows such a normally-on GaAs
It has long been known as a logic circuit using FETs. 1 is a circuit diagram showing an example of the configuration of a set-reset type flip-flop; FIG. In the figure, 100 is a positive logic NOR circuit, and 2
It consists of two GaAs FETs 101 and 102. In exactly the same way, 103 is two GaAs connected in parallel.
This is a positive logic NOR circuit composed of FETs 104 and 105. By applying a set pulse (S) to the gate terminal 106 of the FET 101 and a reset pulse (R) to the gate terminal 107 of the FET 104, the output point of the NOR circuit 100, i.e.
Connection point 10 of each drain of FET101, 102
8 provides the negative phase output ( ) of the flip-flop, and similarly, the positive phase output (Q) is obtained from the connection point 109 between the drains of the FETs 104 and 105 . 1
10 and 111 are NOR circuits 100 and 10, respectively.
3, and one end of each is connected to the positive power supply (+V ₁ ). Note that in the case of integrated circuits, an active load as shown in FIG. 2 is often used, which occupies a smaller area and requires a lower power supply voltage than the linear resistors 110 and 111. 112 and 113 connect the output of one NOR circuit to the other
This is a level shift element to apply DC current at the appropriate level to the input point of the NOR circuit. In the case of integrated circuits, this element consists of several GaAs elements connected in series.
It is common to use a Shiyotoki diode, but
When constructing the circuit of FIG. 1 using discrete elements, other level shift elements (for example, Zener diodes) may also be used. 11
4, 115 is a resistor for supplying the current necessary for normal level shifting from the negative power supply (-V ₂ ). Note that instead of these resistances,
The circuit of FIG. 2 can also be used as a current source element.

Normally-on type as shown in Figure 1
According to a flip-flop that also uses GaAs FETs,
It is possible to operate at ultra high speeds with a clock frequency of 1 GHz or higher. However, in such a high frequency range, the effective gain of the FET decreases due to the input/output capacitance of the FET itself and the parasitic capacitance/inductance of the elements and wiring connected to the FET, so it is necessary to drive the FET under the same conditions as when operating at low speeds. This makes it difficult to obtain a good output waveform. The situation will be briefly explained with reference to FIGS. 3 and 4.

The curve shown by the solid line 300 in FIG. 3 is the small signal open loop gain of the flip-flop in FIG. 107 →
It shows the frequency characteristic of the open gain from the drain output of FET 104 to the output of FET 102 to the output of FET 105. Large gain when the operating frequency is relatively low ( ₁ , e.g. a few hundred MHz)
G ₁ , but as the operating frequency increases ( ₂ ,
(for example, above 1 GHz) the gain decreases (G ₂ ).
Note that since an actual flip-flop performs nonlinear operation with a relatively large signal, its gain characteristics are not necessarily as simple as this, but for the sake of simplicity, it is assumed here that the gain is linear within the operating range.

FIG. 4 shows that a set pulse 40 of constant amplitude is applied to a flip-flop with such an open-loop gain.
FIG. 6 is a diagram showing an output waveform () when a 0 reset pulse 401 is applied. When the interval (T) between the set pulse and reset pulse is short (that is, when the operating frequency is high), the loop gain is small (the third
(corresponding to Figure G ₂ ), the output amplitude of the flip-flop is also small (Figure 4 A), but as the set-reset interval becomes longer (Figure 4 T'), the loop gain increases (corresponding to Figure 3 G ₁ ), and the output pulse The amplitude also increases (Fig. 4 A'). Therefore, when this flip-flop is operated randomly at a clock frequency of 1/T (Hz), the output eye is the fourth eye because the output pulse waveforms of various lengths overlap (shaded area 403 in FIG. 4). As shown in FIG. 402, it becomes small.

To improve the output waveform at high speeds (larger output eye), it is necessary to make the amplitude of the input set/reset pulses larger than during low-speed operation to compensate for the FET's gain reduction in the high range. be. but
It is difficult to supply such large amplitude set/reset pulses at high speeds close to the operating limits of the FET itself, and even if large amplitude set/reset pulses could be generated, the amplitude would be too low.
If the pinch-off voltage of the FET is exceeded,
Since the output impedance increases when the FET is off, the output waveform may even deteriorate.

In this way, the set-reset flip-flop using normally-on GaAs FETs is
Compared to circuits using conventional silicon bipolar transistors, they can operate at higher speeds, but even with such devices, it is unavoidable that the output waveform deteriorates significantly as the speed increases. Ta.

The object of the present invention is to improve the above-mentioned drawbacks of the conventional ultra-high speed set/reset type flip-flop.

That is, according to the present invention, by adding only a few elements to the conventional circuit shown in FIG. 1, it is possible to obtain a good output waveform response over a wide range from low speed to ultra high speed.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment of the set-reset type flip-flop of the present invention. In the figure, 500 is a first two-input NOR circuit consisting of two normally-on GaAs FETs 501 and 502 whose source electrodes are connected in parallel and whose drain electrodes are connected in parallel.
FET→501 The gate electrode 503 is used as the set pulse input terminal, and the drain electrodes 5 are connected to each other.
04 is used as an output terminal (output). Similarly, 505 is a second two-input NOR circuit consisting of two normally-on GaAs FETs 506 and 507 whose source electrodes are connected in parallel and whose drain electrodes are connected in parallel.
A second two-input device in which the gate electrode 508 of the FET 506 is used as a reset pulse input terminal, and the mutually connected drain electrodes 509 are used as output terminals (Q output).
It is a NOR circuit. 510 is the first 2-input NOR
This is a first feedback resistor circuit connected between the output terminal 504 of the circuit 500 and the set pulse input terminal 503, and in this embodiment is composed of a feedback resistor 511 and a DC cutoff capacitor 512. Similarly, 513 is the output terminal 509 of the second 2-input NOR circuit 505 and the reset pulse input terminal 50.
A second feedback resistor circuit is connected between the feedback resistor 514 and the capacitor 515 in this embodiment.

516 and 517 are the load resistances of each two-input NOR circuit like the elements 110 and 111 in FIG.
Level shift elements 520 and 521, which are the same as 2 and 113, are resistors for supplying operating current to the level shift elements, similar to 114 and 115 in FIG.

The circuit shown in FIG. 5 has a simple configuration in which two feedback resistor circuits 510 and 513 are added to the conventional circuit shown in FIG. By determining this, the open loop gain of the flip-flop circuit can be made constant over a wide band as shown by the broken line 301 in FIG. Note that the open loop gain is the output 50 from the set pulse input terminal 503.
4 and the reset pulse input terminal 508
There are two ways, one that leads to Q output 509,
Using four FETs with well-matched characteristics, each pair of load resistors (516 and 517),
Level shift elements (518 and 519), level shift element resistors (520 and 521), feedback resistor (5
11 and 514), capacitor (512 and 515)
If the same values are used, it can be considered that both open loop gains are almost equal.

The flip-flop output waveform when the open loop gain is flat like the curve 301 in FIG.
As shown in the figure. In the figure, the interval between the set pulse 600 and the reset pulse 601 is short (interval T, equivalent to operating frequency ₂ in Fig. 3) and long (interval T', equivalent to operating frequency ₁ in Fig. 3). However, the loop gain remains almost unchanged and becomes a value close to G ₂ .
Therefore, the amplitude of the output pulse 602 at this time is approximately constant (A) regardless of the set/reset pulse interval. Reference numeral 603 indicates the output eye when this flip-flop is operated randomly at a clock frequency of 1/T. There is almost no variation in the output amplitude even for various output pulse widths longer than T, so
A large eye can be obtained even at ultra-high speeds that are close to the operating limits of FETs.

Of course, the output amplitude is constant even when the clock frequency is lower than 1/T, so for set and reset pulses of the same amplitude, this flip-flop has a constant amplitude, low distortion, and stability over a wide operating range from low speed to ultra-high speed. It is possible to generate an output waveform with a

In the embodiment of FIG. 5, since capacitors 512 and 515 are included in each feedback path, negative feedback does not work in the vicinity of DC, and the output amplitude is no longer constant. FIG. 7 shows another embodiment of the present invention. By omitting the capacitors from the feedback resistor circuits 510 and 513 of FIG. 5 and applying feedback to the DC region, the operating range of the flip-flop can be extended from DC to ultra-high speed. This is what I did. Since it is difficult to make a large capacity capacitor in an integrated circuit, this embodiment has a configuration suitable for integration. However, in the case of this embodiment, the feedback resistor circuits 700, 70
Since the drains and gates of FETs 702 and 703 are connected in a direct current manner through 1, it is impossible to independently determine the amount of negative feedback and the gate bias voltage of FETs 702 and 703 as in the embodiment shown in FIG. . Therefore, in this case, for example, FIG.
The ratio of resistors 700 and 704 (resistors 701 and 70
It is necessary to determine the ratio of 5. Furthermore, when the input signal source (the source of the set pulse and reset pulse) of this flip-flop circuit is directly connected to the flip-flop circuit, the bias resistance value is naturally determined in consideration of its output DC level.

As explained above, according to the present invention, it is possible to obtain a set-reset type flip-flop that generates an output waveform with constant amplitude and little distortion over a wide range from low speeds to ultra-high speeds, so it has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the configuration of a conventional set-reset type flip-flop circuit, FIG. 2 is a diagram showing an active load or current source element, FIG. 3 is a diagram explaining the open-loop gain of the flip-flop circuit, and FIG.
5 is a circuit diagram showing an embodiment of the present invention. FIG. 6 is a diagram showing input and output waveforms of the set-reset flip-flop of the present invention.
The figure is a circuit diagram showing another embodiment of the present invention. In the figure, 101, 102, 104, 105 are normally-on GaAs FETs, 100, 103
is a 2-input NOR circuit, 106 is a set pulse input terminal, 107 is a reset pulse input terminal, 108
is the negative phase output terminal, 109 is the positive phase output terminal, 11
0 and 111 are load resistances, 112 and 113 are level shift elements, 114 and 115 are resistors, 300 is the open loop gain of the conventional set-reset flip-flop, and 301 is the open loop of the set-reset flip-flop of the present invention. Gain, 400 is a set pulse, 401 is a reset pulse, 402 is an output eye, 403 is an overlap of output pulse waveforms, 50
0,505 is a 2-input NOR gate, 501,50
2,506,507 is normally-on type GaAs
FET, 503 is a set pulse input terminal, 504,
509 is an output terminal, 508 is a reset pulse input terminal, 510, 513 is a feedback resistance circuit, 511,
514 is a feedback resistor, 512, 515 is a capacitor, 516, 517 is a load resistor, 518, 519
is a level shift element, 520 and 521 are resistors 60
0 is a set pulse, 601 is a reset pulse, 6
02 is the output pulse, 603 is the output eye, 700,
701 is a feedback resistance circuit, 702 and 703 are FETs,
704 and 705 indicate resistances, respectively.

Claims (1)

[Scope of utility model registration request] Two normally-on gallium arsenide field effect transistors (GaAs
FET), the gate electrode of one GaAs FET is the set pulse input terminal, and the mutually connected drain electrodes are the output terminals (output). Consisting of two normally-on GaAs FETs connected in parallel, one GaAs FET's gate electrode serves as a reset pulse input terminal, and the mutually connected drain electrodes serve as an output terminal (Q output). a 2-input NOR circuit; a first level shift circuit connected between the output terminal of the first 2-input NOR circuit and the gate terminal of the other GAas FET of the second 2-input NOR circuit; a second level shift circuit connected between the output terminal of the second two-input NOR circuit and the gate electrode of the other GaAs FET of the first NOR circuit; a first feedback resistor circuit connected between the output terminal and the set pulse input terminal; and a second feedback resistor circuit connected between the output terminal and the set pulse input terminal;
A set-reset flip-flop circuit comprising a second feedback resistor circuit connected between the output terminal of the NOR circuit and the reset pulse input terminal.