JPS633364B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optimal recording bias detection method for a magnetic recording/reproducing machine, and more particularly to an optimal recording bias detection method for automatically detecting and adjusting the optimal recording bias in a two-head tape recorder.

Magnetic tape includes L/H tape, chrome tape,
There are different types of ferrichrome tape, and tape recorders are usually adjusted using the standard tape for each type, but even tapes of the same type have large differences in characteristics, so it is difficult to determine all the recording characteristics for these various tapes. It is difficult to set it optimally.

Conventionally, a tape recorder using a three-head system is known as a device that can automatically set the optimum value of recording bias current for various tapes. However, a three-head tape recorder has a separate recording head, playback head, and erase head, and the recording head records the signal while the playback head plays it back to find the optimum value. Therefore, there is a time lag between when a signal is recorded by the recording head and when the signal is reproduced by the reproduction head. Therefore, the three-head tape recorder has the disadvantage that the recording bias current is detected with a slight deviation from the optimum value.

An object of the present invention is to provide a two-head tape recorder equipped with a single head for recording and playback, and an erasing head, so that the recording bias current can be reduced without causing the shift unlike the conventional tape recorder. An object of the present invention is to provide an optimal recording bias detection method that can accurately set an optimal value.

The optimal recording bias detection method of the present invention first fixes the recording signal level to a predetermined value, records while sequentially varying the recording bias current value between the upper and lower limits in multiple steps, and then The playback level of the recording signal at each of a plurality of variable steps is stored in a predetermined storage means while sequentially playing back from the first step of the current value, and the maximum value is detected from among the playback levels thus stored. The recording bias current value corresponding to the current value is set as the optimum recording bias.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit block diagram for an embodiment of the present invention, in which a mid-low frequency signal f _L (333Hz) for recording bias and recording level adjustment and a high frequency signal f _H for recording equalizer (EQ) adjustment are shown. (10KHz) is selectively selected by the changeover switch 1 and input to the line switch 2. The line switch 2 selects either the line input signal or the aforementioned adjustment signal (f _L or f _H ) and applies it to the flat amplifier 3. The amplified signal is input to the recording level setting circuit 4, and its level is varied and set to an appropriate level. Thereafter, the signal is applied to the recording equalizer setting circuit 5.

This circuit 5 has a configuration in which the equalizer characteristics are variable, and its output is the recording bias signal f _B
(100KHz) and record/playback switch 10
The data is recorded onto a tape 7 by the R/P head 6 via the R/P head 6.

The recording bias f _B is applied to a recording bias setting circuit 8 for varying and appropriately setting the bias current value, and its output is superimposed on the recording signal.

The tape recording signal is reproduced by the R/P head 6, amplified by the reproduction amplifier 11 via the switch 10, and then inputted to the detection circuit 15. In this detection circuit, the reproduced signal is converted to a DC level and becomes one input of the comparator 16. The output of a D/A converter 17 is used as the reference signal which is the other input to this comparator 16, and this converter converts the parallel binary digital signal output from the port output P _A of the microprocessor 18 into a DC level. It is something. The output of comparator 16 is applied to port input P ₁ of microprocessor 18.

Binary digital signals are output from the port outputs P _B , P _C , and _PD of the processor 18, respectively, and these signals are sent to the recording level setting circuit 4 and the EQ.
Control signals 101, 102 and 103 are used to control the setting circuit 5 and bias setting circuit 8.

Changeover switch 1, line switch 2 and R/P
The switches 10 are controlled on/off by the port outputs P ₂ , P ₃ and P ₄ of the processor 18, and the port output P ₅ is used as a control signal to control the mechanical system of the tape recorder. Similarly, control signals from the mechanical system are input to _P6 .

A memory 19 including a ROM in which a program for controlling the microprocessor 18 is stored in advance and a readable/writable RAM is provided, and a keyboard 20 is connected to provide external commands. The keyboard 20 may be provided with a display so that the control status of the microprocessor can be monitored. Note that during normal operation, the RAM of the memory 19 is supplied with power from the device power supply, but when the power is cut off, it is configured to be powered from a so-called backup power supply such as a battery, so that the stored contents cannot be saved. It is possible to maintain it at all times.

FIG. 2A shows a specific example of the recording level setting circuit 4, in which the impedance between the input/output line and ground is varied by a parallel 6-bit digital control signal 101 from the microprocessor 18. For this purpose, a switching transistor Q, a resistor network R, 2R,..., 32R and a D-FF
It is made up of. In the figure B, control signal 10
The input/output ratio of the recording level corresponding to 1 is shown.

The magnitude of the 6-bit control signal 101 is the minimum value 00 (H)
~ The maximum value is 3F (hexadecimal display), which is digitally represented in 64 steps, and 00 (H) is the control signal 101.
is (000000), indicating step 0, 3F is (111111), indicating step 63, and 20(H) indicates the intermediate step (100000). Here, the recording level is changed stepwise in 64 steps using a 6-bit control signal, but increasing the number of bits widens the variable range and increases resolution. Note that (H) indicates that the signal is expressed in hexadecimal notation, and the same applies to the other control signals 102 and 103.

FIG. 3A shows a specific circuit example of the recording bias setting circuit 8, which changes the resistance value between the bias signal line and the ground according to the 6-bit control signal 103 of the processor 18. It consists of networks R, 2R, . . . , 32R, D-FF, inverter INV, etc. 801 indicates a bias amplifier that amplifies 100KHz. FIG. 5B shows how the bias signal current changes with respect to the control signal 103.

FIG. 4A shows a specific example of the recording equalizer setting circuit 5, which changes the value of the capacitive element _Cs for equalizer characteristics in accordance with the control signal 102 of the processor 18 to appropriately select the amount of compensation for the 10 KHz signal. It consists of an operational amplifier OP, a switching transistor Q, a capacitor network C, 2C, . . . , 32C, D-FF, etc. B in the same figure shows the change in the capacitance value for the digital control signal 102, and C shows the frequency characteristic of the digital control signal 102, that is, the recording signal current with the capacitance value as a parameter.

The operation of the present invention will be explained below using FIGS. 5 to 7.

First, by pressing a "START" button (not shown) on the keyboard 20, a start signal for automatic adjustment is input from the keyboard to the microprocessor 18. In response to this start signal, the operation is started according to the procedure indicated in the program stored in the ROM in the memory 19.

First, the switch 2 is controlled by the port output _P3 of the processor 18 to disable line input, and the mechanical system is put into the recording state by the port output _P5 . At this time, switch 10 also has port output
The recording state is switched by _P4 , and the selection switch 1 is controlled by the port output _P2 to select the signal _fL . The data previously stored in the RAM is outputted from port outputs P _B , P _C , and _PD to control the recording level setting circuit 4, EQ setting circuit 5, and bias setting circuit 8 to their standard states.

In this state, as shown in _FIG.
The mid-low frequency signal f _L is recorded at a standard level between times t _{1 and t} 1 , and no signal is recorded between times t ₁ and _{t 2} . During this period, the bias is at the standard value as shown by the dotted line.
This period _t0 to _t2 is for recording a so-called marker signal for detecting the starting point position for the next reproduction stage.

Between times _t2 and _t3 , the signal f _L is again fixed at the standard level, and the bias current is varied from the minimum to the maximum as shown by the dotted line in the figure, that is, the control signal 103 is changed from 00(H) to 3F. Record the changes sequentially in 64 steps up to (H). Thereafter, the tape is stopped at time _t3 , and the tape is rewound to the part where the start signal is recorded (corresponding to _t0 ) and brought to a stopped state. This stop position can be stored in the internal memory of the microprocessor 18 or the external memory 19.

Next, the camera system is controlled to the playback state, and the R/P switch 10 is switched to the playback side. Here, from the port output P _A, for example, the minimum value of the digital signal
00(H) is output and the minimum DC level is applied by the D/A converter 17 as a reference input to the comparator 16. Therefore, at time _t4 , the comparator output is inverted, confirming the rise of the reproduced signal _fL , and ending the period.
It is in a standby state from _t4 to _t6 .

At this time, the rise of the reproduction signal f _L may be confirmed by the output of the comparator, and the period t ₅ to _{t 6} may be set as a standby state.

At time _t6 , the reproduction level of the signal f _L is A/D converted by a so-called successive approximation type A/D converter consisting of a comparator 16 and a D/A converter 17.
Convert it into a digital signal. Therefore, the period t ₆ ~
The reproduction level for each step of _t7 is converted into a digital signal and stored in each predetermined location in the RAM.

Thereafter, digital signals corresponding to the respective stored playback levels are sent to the microprocessor 1.
8, the digital signal corresponding to the maximum level is detected. The recording bias current value corresponding to this level is the optimum recording bias. The recording bias current value at this time can be easily determined, for example, by associating each storage address of each digital signal with the variable step number during recording.

At this time, the tape is rewound again to the starting position in preparation for the next adjustment step.

The recording bias current value thus set can be changed by pressing a predetermined switch on the keyboard 20.
It can be stored in RAM and read out using similar operations.

Next, the recording level is adjusted as shown in FIG. That is, the mid-low frequency signal f _L is selected and set to the standard level, and the EQ setting circuit 5 and bias setting circuit 8 are also set and controlled to be in the standard state. Then, the same operation as at times _t0 to _t2 in FIG. t ₃ than ₂
In the meantime, the control signal 101 is sequentially varied in 64 steps to record the recording level of the signal _fL from the minimum to the maximum. Thereafter, from time _t3 to time _t7 , the same operation as that shown in FIG. 5 is performed.

And at time t ₇ all playback signal levels
After f _L is digitally stored, a predetermined reference level E previously stored in the memory and these digital reproduction signals are compared in the microprocessor, and a digital signal equal to the reference level E is detected. . The recording level corresponding to the digital signal at that time is the optimum value, and the recording level at this time can also be determined by making each storage address of each digital signal correspond to the number of variable steps during recording. . At this time, the tape is rewound to the starting position again.

The recording level thus set can be stored in the RAM and read out.

Finally, the EQ characteristics are adjusted as shown in FIG. That is, the high frequency signal _fH is selected and set to the standard level, and the recording level setting circuit 4 and bias setting circuit 8 are also controlled to be in the standard state. Then, exactly the same operation as at times t ₀ to _{t 2} in FIG. 5 is performed, and then the bias setting circuit 8
and recording level setting circuit 4 is controlled and set by control signals 103 and 101 to the previously detected optimum value, and control signal 1 is set from time t ₂ to t ₃ .
02 is made variable in 64 steps, and recording is performed by varying the amount of recording compensation for the high frequency signal _fH . Thereafter, from time _t3 to time _t7 , the same operation as that shown in FIG. 5 is performed.

And at time t ₇ all playback signal levels
After f _H is digitally stored, the reference level E previously stored in the memory and these digital signals are compared in the microprocessor, and a digital signal equal to the reference level E is detected. The recording compensation amount corresponding to the digital signal at that time indicates the optimum value, and the optimum recording EQ characteristic can be obtained.

Finally, the tape returns to the starting position and stops, the line input inhibition is canceled, and the normal state is restored.

In the above embodiment, the recording bias, level, etc. are varied in ascending order from the minimum step to the maximum step, but the order of variation is not limited to this, and may be varied as appropriate from the minimum to the maximum step. Bye.

As described above, according to the present invention, a two-head tape recorder is used in which a single head is used for both recording and playback, and a marker signal is recorded to detect the starting point position of the recorded signal. This configuration has the advantage that the recording bias current can be set accurately without the disadvantage of deviation from the optimal value that occurs when detecting the optimal recording bias current with a 3-head tape recorder. .

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram for an embodiment of the present invention, Fig. 2A is a diagram showing an example of a recording level setting circuit, B is a characteristic diagram thereof, and Fig. 3A is an example of a recording bias setting circuit. Figure 4A shows its characteristic diagram.
is a diagram showing an example of an EQ setting circuit, B and C are its characteristic diagrams, Figure 5 is an operation explanatory diagram for recording bias adjustment, Figure 6 is an operation explanatory diagram for recording level adjustment, and Figure 7 is an explanatory diagram of operation for EQ adjustment. Explanation of symbols of main parts, 4... Recording level setting circuit, 5... EQ setting circuit, 8... Recording bias setting circuit, 18... Microprocessor, 19...
…memory.

Claims (1)

[Claims] 1. In a two-head tape recorder in which a single head is used for both recording and playback, a marker signal for detecting a starting point position is recorded, and the level of a recording signal of a single frequency is recorded. is set to a predetermined value, recording is performed while sequentially varying the recording bias current value in multiple steps between the upper limit and the lower limit, and then, following the reproduction of the marker signal, the first step of the recording bias current value is changed. converting the playback level of the recording signal in each of the steps into a digital signal by a successive approximation type analog/digital converter while sequentially playing back from the beginning, and storing the digital signal in a predetermined memory address of the storage means, This is achieved by detecting a digital signal corresponding to the maximum value of the reproduction level stored in a predetermined storage address of the means, and by associating each storage address of the digital signal with the variable step number at the time of recording in advance. A method for detecting an optimal recording bias for a magnetic recording/playback device, characterized in that a recording bias current value corresponding to the maximum value is determined and this is set as the optimal recording bias.