JPS633513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for correcting convergence in a color television receiver, which allows accurate adjustment, and
Another object of the present invention is to provide a digital convergence device that is easy to adjust.

A shadow mask color cathode ray tube (hereinafter referred to as CRT) used in general color television receivers.
As is well known, it has three electron guns: red, green, and blue. However, it is structurally impossible to place all of these multiple electron guns on the central axis of the CRT, so they are placed a little away from the central axis.
It is also installed slightly tilted inward with respect to the central axis. Therefore, on the screen on this central axis, each electron beam converges at the shadow mask, and simultaneously emits red, green, and blue fluorescent dots through the same hole, resulting in a convergence state. However, since the radius of curvature of the shadow mask is larger than the distance from the center of deflection to the center of the shadow mask, the three electron beams converge in front of the shadow mask at locations other than the central axis of the CRT. Therefore, the three electron beams cannot pass through the same hole at the same time, and the color shift, or convergence shift, of the reproduced image increases as it moves away from the center of the screen. In order to prevent such problems, it is necessary to perform convergence correction so that the three electron beams converge at the shadow mask over the entire screen.

Generally, a method is used to obtain a convergence correction waveform in an analog manner using passive elements such as L, C, and R from the horizontal flyback pulse and vertical deflection waveform, but there are problems in terms of convergence accuracy. be. On the other hand, as a method of performing convergence with higher precision, a method of digitally performing convergence correction has been proposed, for example, as shown in US Pat. No. 3,943,279.

In the conventional example described above, the concept is to project a convergence correction pattern such as dots on the screen, digitally write the convergence correction amount data for each point in one frame memory, read out this information, and then /A conversion and convergence correction. Figure 1 below,
This will be explained in detail based on FIG.

First, as shown in FIG. 2, a dot generator 16 displays adjustment points on the screen in, for example, 13 rows in the horizontal direction and 9 columns in the vertical direction. Use the cursor keys 17 on the control panel 1 to select the adjustment point where you want to adjust. The address of the adjustment point selected with the cursor key 17 is stored in the cursor counter 13. Next, press the data write key 18 for the color you want to correct, for example red, and set the desired data on the data reversible counter 2 while looking at the screen.
The output is written to the address specified by the cursor counter 13 in the one frame memory 3. The contents of the one frame memory 3 at the address selected by the cursor counter 13 are read out to the data reversible counter 2, and when it is desired to further increase the convergence correction amount, the contents of the data reversible counter 2 are increased and Conversely, when you want to decrease
Write correction is performed by decrementing the contents of the data reversible counter 2 and writing desired data into the one frame memory 3. The same procedure is repeated for all adjustment points on the screen.

Next, reading out the convergence correction amount written in the one-frame memory 3 will be explained. Since the one-frame memory 3 only has correction data for locations corresponding to adjustment points, it is necessary to perform interpolation for each scanning line between adjustment points in the vertical direction. Therefore, for example, after reading the correction data for the adjustment point in the first column from the 1-frame memory 3 and setting it in the register 4 for 1 horizontal scanning period (1H),
The correction data of the adjustment points in the second column is read out from the frame memory 3, and the correction data of the adjustment points in the first column and the second column are read out from the frame memory 3. The amount of correction in the scanning line included between the adjustment points in the column is determined by interpolation. That is,
The difference between the correction amount in the first column and the correction amount in the second column is obtained by the subtraction circuit 5, and the weighting coefficient for each scanning line written in advance in the coefficient ROM 7 is applied to the multiplication circuit 6.
The result and the correction amount in the second column are added together in the adding circuit 8 to perform interpolation. Next, adder circuit 8
The output signal is converted into an analog quantity by a D/A converter 9, smoothed by a low pass filter (LPF) 10,
After amplification, it is supplied to the convergence yoke. The same applies to the other green, blue radials, and blue laterals.

In the conventional apparatus described above, since each adjustment point can be corrected independently, convergence correction can be performed with high accuracy. However, for example, if an overall color shift occurs statically for some reason, it may be possible to add or subtract a certain amount of correction across all adjustment points, but with the above device, each adjustment The amount of correction must be corrected point by point, and the large number of adjustment points is troublesome, making adjustment time consuming and extremely inconvenient.

The present invention therefore seeks to provide a digital convergence device that does not have the above-mentioned drawbacks. An embodiment of the present invention will be described in detail below based on the drawings.

First, FIG. 3 shows a conceptual diagram of an embodiment of a digital convergence device according to the present invention. In FIG. 3, 21 is a video signal input terminal, and the video circuit 22 amplifies the incoming video signal to the required amplitude.
Drives CRT23. The video circuit 22 operates in the same way as a normal receiver, but is supplied with a dot or crosshatch signal indicating the adjustment point created by the digital convergence circuit 27, which is displayed during convergence adjustment. 25 is a deflection circuit, and 29 is a deflection yoke, which deflects the electron beam of the CRT 23 in response to a synchronization signal arriving at the synchronization signal input terminal 24. The control panel 26 is equipped with keys necessary for convergence adjustment, such as a cursor key for instructing which position on the screen to perform convergence correction, and a key for writing the correction amount into the digital convergence circuit.

The digital convergence circuit 27 includes a one-frame memory composed of non-volatile memory, stores convergence correction data from the control panel 26, reads out this data, amplifies the current in the output circuit 28, and sends the correction current to the convergence coil 30. to correct convergence.

Note that the digital convergence circuit 27 is
Since it is necessary to operate in synchronization with the deflection, a synchronization signal is supplied.

FIG. 4 shows a block diagram of the main parts of the control panel 26 and the digital convergence circuit 27.
Components corresponding to those in FIG. 1 are indicated by the same numbers.
In order to make it easier to understand, the convergence of a receiver using a CRT with a delta-type electron gun arrangement will be described below. Furthermore, the number of dots or crosshatches for convergence adjustment is 13 rows vertically and 9 columns horizontally on the screen, as shown in FIG.

First, the correction for each adjustment point will be described. At this time, the operation of the switching circuit 31 connects the write key 18 and the data reversible counter 2, and the operation during this correction is the same as the conventional example, but the fourth
This will be explained using figures. control panel 26
As shown in FIG. 2, use the cursor keys 17 provided to select which position of the convergence correction amount of the adjustment points displayed on the screen is to be written to the one-frame memory 3, and at the same time select the color using the write key 18. Assume that you have selected red. Note that this cursor key 17 can be moved one dot at a time up, down, left and right so that any adjustment point displayed on the screen can be selected. Further, the write key 18 is used to write the convergence correction amount into the one frame memory 3.

The address of the dot selected by the cursor key 17 on the one frame memory 3 is stored in the cursor counter 14;
The output signal is added to the 1-frame memory 3 via the address multiplexer 11, and the correction amount written in the 1-frame memory 3 is read out and set in the data reversible counter 2 during the retrace period of the receiver. One frame memory 3 is composed of non-volatile RAM, and its capacity is 13 horizontal dots x 9 vertical dots, and if the correction amount is, for example, 8 bits, red,
There are four types of correction: green, blue radial, and blue lateral, so the total is 13 x 9 x 8 x 4 bits.

The data reversible counter 2 is used to write the data of the convergence correction amount to the 1-frame memory 3 and to modify the contents written to the 1-frame memory 3. When increasing the amount,
When increasing the content of the data reversible counter 2 and decreasing the correction amount, the content of the data reversible counter 2 is decreased and this output signal is sequentially written into the one frame memory 3. Do the same for all the points you want to correct.

Next, a case will be described in which a certain convergence correction amount N' bits is added over all adjustment points. When the full screen key 35 of the control panel 26 is operated, the switching circuit 31 connects the write key 18 and the N'-bit data reversible counter 32, and the N'-bit correction amount from the write key 18 is transferred to the data reversible counter 32. It is set to 32. This data reversible counter 32 writes and corrects the correction amount in a constant value memory 33 composed of a non-volatile RAM with a capacity of at least N' bits for storing a certain constant convergence correction amount over all adjustment points. Its operation is similar to that of the data reversible counter 2 described above. The required capacity of the constant value memory 33 is N'×4 bits since there are four types of correction: red, green, blue radial, and blue lateral.

As described above, the correction amount corresponding to each adjustment point in the 13th row and 9th column shown in FIG. 2 is written into the 1 frame memory 3 and the 1 constant value memory 33, and convergence correction is performed at each adjustment point. However, no correction is made between adjustment points. Therefore, if we assume that there are M scanning lines between adjustment points in the vertical direction, the correction amount of adjustment points written in the 1-frame memory 3 corresponds to M scanning lines between adjustment points with no data. It is necessary to generate correction data. So, for example, set the correction amount for the adjustment point in the first column to 1.
Read from frame memory 3, 1H register 4
After setting, the correction amount of the adjustment point in the second column is read from the one frame memory 3, the difference between the correction amount in the first column and the correction amount in the second column is determined by the subtraction circuit 5, and the difference is calculated by the subtraction circuit 5. A multiplier circuit 6 multiplies the weighting coefficient for each scanning line, which is written in advance, to obtain a variation for each scanning line, and an addition circuit 8 adds this variation and the correction amount in the second column to calculate the internal value. By performing interpolation, the amount of correction for each scanning line is determined. On the other hand, the contents of the constant value memory 33 are read out repeatedly in synchronization with scanning, horizontally at the timing of each adjustment point, and vertically at each scanning line. Next, adder circuit 8
Correction amount and constant value memory 3 for each adjustment point of the output of
The output signals of 3 are added by an adder circuit 34, and the output signal of the adder circuit 34 is converted into an analog quantity by a D/A converter 9. Since the output signal waveform of the D/A converter 9 has a stepwise waveform, it is smoothed by a low-pass filter (LPF) 10 for correction between adjustment points in the horizontal direction to obtain a smooth convergence correction waveform.

Note that since the operation of the one-frame memory 3 needs to be performed in accordance with the screen, the control circuit 12 is supplied with horizontal and vertical synchronization signals.

FIG. 5 shows another embodiment, in which the adder circuit 3
4 is inserted between the 1 frame memory 3 and the 1H register 4, and the output signal of the 1 frame memory 3 and the output signal of the constant value memory 33 are added together, and then interpolation processing and D/A conversion are performed. be. It is clear that similar results can be obtained with the embodiment shown in FIG. The convergence correction for red has been described above, but the same applies to green and blue.

In the above embodiment, a CRT with a delta-type electron gun arrangement has been described, but it is also applicable to a CRT with an in-line electron gun arrangement, or a projection TV receiver that uses multiple projection CRTs to configure a large screen TV. It goes without saying that the idea of the present invention is also effective.

As is clear from the above description, the present invention has the function of performing convergence correction independently for each adjustment point, and the function of performing a certain amount of correction across all adjustment points, so that static When correcting deviations, there is no need to write the correction amount for each adjustment point, saving adjustment time and greatly improving operability. In addition, the present invention is an excellent digital convergence device that is industrially advantageous because it has the advantage that the memory capacity for storing a fixed correction amount is small because only one correction amount is required.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional digital convergence device, FIG. 2 is a front view of a picture tube showing the projected state of convergence adjustment dots, and FIG. 3 is a configuration diagram showing an embodiment of the digital convergence device of the present invention. , FIG. 4 is a configuration diagram of the main parts of this embodiment, and FIG.
The figure is a main part configuration diagram of another embodiment. 3...1 frame memory, 4...1H register, 5
...Subtraction circuit, 6...Multiplication circuit, 7...Coefficient ROM, 8
...Addition circuit, 9...D/A converter, 10...LPF,
11... Multiplexer, 12... Control circuit, 13...
Cursor counter, 14... Comparator, 15... Read address counter, 26... Control panel, 27... Digital convergence circuit, 28
...Output circuit, 30...Convergence yoke, 31
...Switching circuit, 32...Data reversible counter, 33...
Constant value memory, 34...addition circuit.

Claims (1)

[Claims] 1 One frame memory having a capacity of at least m×n×N bits in which to digitally write the individual convergence correction amounts of adjustment points in m rows and n rows with N bits at each point; a constant value memory composed of a non-volatile RAM having a capacity of at least N' bits for adding to the output signal of the one-frame memory; and a constant value memory for writing correction amounts into the constant value memory for correction. ' A reversible data counter of bits, a signal interpolated for each scanning line between adjustment points in the vertical direction, or an adder circuit that adds the output signal of the one frame memory and the output signal of the constant value memory. A digital convergence device characterized by: