JPS6337417B2 - - Google Patents
Info
- Publication number
- JPS6337417B2 JPS6337417B2 JP55055071A JP5507180A JPS6337417B2 JP S6337417 B2 JPS6337417 B2 JP S6337417B2 JP 55055071 A JP55055071 A JP 55055071A JP 5507180 A JP5507180 A JP 5507180A JP S6337417 B2 JPS6337417 B2 JP S6337417B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- write
- memory
- circuit
- memory element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5507180A JPS56153590A (en) | 1980-04-25 | 1980-04-25 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5507180A JPS56153590A (en) | 1980-04-25 | 1980-04-25 | Storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56153590A JPS56153590A (en) | 1981-11-27 |
| JPS6337417B2 true JPS6337417B2 (2) | 1988-07-25 |
Family
ID=12988458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5507180A Granted JPS56153590A (en) | 1980-04-25 | 1980-04-25 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56153590A (2) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100852191B1 (ko) | 2007-02-16 | 2008-08-13 | 삼성전자주식회사 | 에러 정정 기능을 가지는 반도체 메모리 장치 및 에러 정정방법 |
-
1980
- 1980-04-25 JP JP5507180A patent/JPS56153590A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56153590A (en) | 1981-11-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112837725B (zh) | 半导体存储器件和操作半导体存储器件的方法 | |
| KR102658230B1 (ko) | 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법 | |
| US9087614B2 (en) | Memory modules and memory systems | |
| KR102787324B1 (ko) | 반도체 메모리 장치 및 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법 | |
| US4319356A (en) | Self-correcting memory system | |
| US4953164A (en) | Cache memory system having error correcting circuit | |
| CN114121075B (zh) | 用于存储器刷新的系统及方法 | |
| US10528270B2 (en) | Memory system having nonvolatile memory and volatile memory and processor system | |
| US7861138B2 (en) | Error correction in memory devices | |
| KR102883335B1 (ko) | 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법 | |
| JPH0118459B2 (2) | ||
| US11276456B2 (en) | Systems and methods for capture and replacement of hammered word line address | |
| US6853602B2 (en) | Hiding error detecting/correcting latency in dynamic random access memory (DRAM) | |
| US20240428842A1 (en) | Apparatuses and methods for multiple types of alert along alert bus | |
| JPH0724158B2 (ja) | 記憶装置 | |
| US12505011B2 (en) | Memory controller and memory system including the same | |
| JP2623687B2 (ja) | 自己訂正機能付きlsiメモリ | |
| JPS6337417B2 (2) | ||
| JPH0991206A (ja) | メモリ制御装置およびメモリ検査方法 | |
| IE49719B1 (en) | Method of testing the operation of an internal refresh counter in a random access memory and circuit for the testing thereof | |
| JP3092806B2 (ja) | ダイナミック型ランダムアクセスメモリ | |
| JP2699640B2 (ja) | 放射線認識回路を用いた電子回路 | |
| JPS63187500A (ja) | 半導体記憶装置 | |
| US10255986B2 (en) | Assessing in-field reliability of computer memories | |
| JP2627491B2 (ja) | 半導体記憶装置 |