JPS6337498B2 - - Google Patents
Info
- Publication number
- JPS6337498B2 JPS6337498B2 JP55012496A JP1249680A JPS6337498B2 JP S6337498 B2 JPS6337498 B2 JP S6337498B2 JP 55012496 A JP55012496 A JP 55012496A JP 1249680 A JP1249680 A JP 1249680A JP S6337498 B2 JPS6337498 B2 JP S6337498B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- wire bonding
- semiconductor
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07521—Aligning
- H10W72/07523—Active alignment, e.g. using optical alignment using marks or sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明はプリント回路基板に直接半導体ペレツ
トを実装するようにした半導体装置において、プ
リント回路基板の改善を図ると共に、ワイヤボン
デイング方法の改善を図るようにしたものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention aims to improve the printed circuit board and the wire bonding method in a semiconductor device in which semiconductor pellets are directly mounted on the printed circuit board.
半導体装置の中でも半導体ペレツトを直接プリ
ント回路基板(プリンテイツド・サーキツト・ボ
ード、PCBと称す)に実装するものは、半導体
装置全体を小型かつ薄型に形成できる利点を有す
るため、腕時計等の小型機器に用いられる。この
種の半導体装置は、例えば第1図及び第2図に腕
時計用のものを例示するように、所定の形状に形
成したガラスエポキシ基板1の表面や裏面に銅箔
を用いてリード等を含む回路2を形成しておき、
一方このガラスエポキシ基板1の一部に半導体ペ
レツト3を固着し、このペレツト3の電極パツド
4と前記回路(リード)2との間にワイヤ5をボ
ンデイングした後、レジンにてペレツト3やワイ
ヤ5をモールド封止するようにしたものである。 Among semiconductor devices, those in which semiconductor pellets are directly mounted on a printed circuit board (referred to as a printed circuit board, PCB) have the advantage that the entire semiconductor device can be made small and thin, and are therefore used in small devices such as wristwatches. It will be done. This type of semiconductor device includes leads etc. using copper foil on the front and back surfaces of a glass epoxy substrate 1 formed into a predetermined shape, as shown in FIGS. 1 and 2 for example for wristwatches. Form circuit 2,
On the other hand, a semiconductor pellet 3 is fixed to a part of this glass epoxy substrate 1, and a wire 5 is bonded between the electrode pad 4 of this pellet 3 and the circuit (lead) 2, and then the pellet 3 and wire 5 are bonded with resin. It is designed to be sealed with a mold.
ところで、前記した電極パツド4とリード2と
の間にワイヤボンデイングを行なう場合、近年で
は、自動的にボンデイングを行なうようにしてい
る。即ち、ペレツト3上に形成した電極パツドや
プリント回路基板1上に形成したリード等は夫々
写真技術を利用して形成しているため、各々はペ
レツトやプリント回路基板上での位置が一定して
おり、自動化に向いているからである。 By the way, in recent years, when wire bonding is performed between the electrode pad 4 and the lead 2, the bonding is automatically performed. That is, since the electrode pads formed on the pellet 3 and the leads formed on the printed circuit board 1 are formed using photographic technology, their positions on the pellet and printed circuit board 1 are constant. This is because it is suitable for automation.
ところが、プリント回路基板1上への半導体ペ
レツト3の固着は必ずしも一定位置となるわけで
はないため、これら両者の相対位置の誤差によつ
て前記電極パツドとリードとの相対位置にもずれ
が生じることになる。このため、従来では、電極
パツド4とリード2の位置をボンデイング前に
夫々コンピユータにより検出記憶しておき、この
データに基づいて自動ボンデイングを行なうよう
にしている。この場合電極パツドの位置検出に際
しては、各パツドが微少サイズに形成されてこれ
を点として認識することができるので、各パツド
の中から任意のパツドを2個以上選択してその位
置を検出すればペレツト全体の位置が特定でき、
これから全てのパツド位置を比較的容易にしかも
自動的に検出できる。ところが、リード側の位置
検出にあつては、各リードの幅や長さ寸法はワイ
ヤボンデイングの作動幅を考慮して比較的大きく
形成しているため、これを点として認識すること
は困難であり、したがつてリード位置を自動的に
検出することはできない。 However, since the semiconductor pellet 3 is not necessarily fixed on the printed circuit board 1 in a fixed position, an error in the relative position between the two may cause a deviation in the relative position between the electrode pad and the lead. become. For this reason, conventionally, the positions of the electrode pads 4 and leads 2 are detected and stored by a computer before bonding, and automatic bonding is performed based on this data. In this case, when detecting the position of the electrode pads, each pad is formed into a minute size and can be recognized as a point, so it is necessary to select two or more arbitrary pads from among each pad and detect their position. The entire pellet can be located,
From now on, all pad positions can be detected relatively easily and automatically. However, when detecting the position on the lead side, the width and length of each lead are made relatively large considering the working width of the wire bonding, so it is difficult to recognize this as a point. , therefore the lead position cannot be detected automatically.
このため、リード位置、換言すればプリント回
路基板の位置の決定に際しては作業者がTVカメ
ラ等を利用して目視により位置決めをせざるを得
ず、ワイヤボンデイングの全自動化の障害になつ
ているのが実情である。 For this reason, when determining the lead position, or in other words, the position of the printed circuit board, workers are forced to visually determine the position using a TV camera, etc., which is an obstacle to fully automating wire bonding. is the reality.
したがつて本発明の目的は、ワイヤボンデイン
グを全自動的に行なうことができる半導体装置の
プリント回路基板及びこのプリント回路基板を用
いたワイヤボンデイング方法を提供することにあ
る。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a printed circuit board for a semiconductor device that can perform wire bonding fully automatically, and a wire bonding method using this printed circuit board.
本発明の要旨は、電極パツドを有しその平面形
状が四角形の半導体ペレツトと、前記半導体ペレ
ツトを固定するためのベース(例えば、プリント
回路基板)と、前記ベース上に設けられたワイヤ
ボンデイング部(例えば、リードの先端部)を有
し、前記半導体ペレツトと前記ワイヤボンデイン
グ部間にワイヤボンデイングを施すようにした半
導体装置において、前記ベースに固定された前記
半導体ペレツトの第一の角部近傍であつて前記ベ
ース上に光学的に認識可能な第一の位置認識用パ
ツドを設け、前記半導体ペレツトの第二の角部近
傍であつて前記ベースに光学的に認識可能な第二
の位置認識用パツドを設けたことを特徴とする半
導体装置にある。 The gist of the present invention is to provide a semiconductor pellet having an electrode pad and a rectangular planar shape, a base (for example, a printed circuit board) for fixing the semiconductor pellet, and a wire bonding portion (for example, a printed circuit board) provided on the base. For example, in a semiconductor device having a wire bonding portion (the leading end of a lead) and wire bonding between the semiconductor pellet and the wire bonding portion, the wire bonding portion may be located near a first corner of the semiconductor pellet fixed to the base. a first position recognition pad that is optically recognizable on the base, and a second position recognition pad that is optically recognizable on the base and is located near a second corner of the semiconductor pellet. A semiconductor device is provided.
以下、本発明の実施例を図面に基づいて説明す
る。 Embodiments of the present invention will be described below based on the drawings.
第3図は本発明のプリント回路基板の要部平面
図、第4図はその断面図である。プリント回路基
板10は、ガラスエポキシ基板を主体とし、この
基板の表面、裏面に銅箔を用いて所定の回路12
を形成している。そして、このプリント回路基板
10の表面一部には厚さ方向に凹所11を形成し
ており、この凹所11内に半導体ペレツト13を
銀ペースト16等により接着している。この凹所
11の周囲には、半導体ペレツト13に形成した
複数個の電極パツド14との間にワイヤ15を結
線するリード12aを周方向に配設し、前記回路
12と一体的に銅箔にて形成している。そして、
本発明にあつては、前記リード12a近傍の少な
くとも2箇所、本実例では3箇所に夫々微少サイ
ズの方形の位置認識用パツド17を形成している
のである。このパツド17は前記リード12aや
回路12の形成時に、リードや回路の一部として
一体的に銅箔にて形成することができる。またこ
のパツド17のサイズは、パツド17位置を点と
して認識できる程度の大きさが好ましく、本実施
例では0.1〜0.5mm□の大きさに設定している。図
中、18はプリント回路基板の裏面に形成したバ
ツテリ電極である。 FIG. 3 is a plan view of essential parts of the printed circuit board of the present invention, and FIG. 4 is a sectional view thereof. The printed circuit board 10 is mainly made of a glass epoxy board, and a predetermined circuit 12 is formed using copper foil on the front and back sides of this board.
is formed. A recess 11 is formed in a part of the surface of the printed circuit board 10 in the thickness direction, and a semiconductor pellet 13 is adhered into the recess 11 with silver paste 16 or the like. Around this recess 11, leads 12a for connecting wires 15 to a plurality of electrode pads 14 formed on the semiconductor pellet 13 are disposed in the circumferential direction, and are integrally formed with the circuit 12 in copper foil. It is formed by and,
In the present invention, microscopic rectangular position recognition pads 17 are formed at at least two locations near the lead 12a, three locations in this example. This pad 17 can be integrally formed of copper foil as a part of the lead or circuit when the lead 12a or circuit 12 is formed. The size of the pad 17 is preferably such that the position of the pad 17 can be recognized as a point, and in this embodiment, the size is set to 0.1 to 0.5 mm square. In the figure, 18 is a battery electrode formed on the back surface of the printed circuit board.
次に以上のように構成したプリント回路基板を
利用したワイヤボンデイング方法を説明する。 Next, a wire bonding method using the printed circuit board configured as described above will be explained.
プリント回路基板10の凹所11内に半導体ペ
レツト13が固着されると、第5図に示すよう
に、TVカメラ19とコンピユータ20を結合さ
せた位置検出装置21が作動される。この装置2
1は、半導体ペレツト13の電極パツド14や、
プリント回路基板10の位置認識パツド17の中
から夫々選択された2以上の電極パツド14a
(第3図)や位置認識パツド17の位置を検出す
るものであり、これら各パツド14a,17の位
置を検出したときにはこれから半導体ペレツト1
3とプリント回路基板10との相対位置関係を検
出することができる。そして、両者の相対位置関
係を検出した後には、予めコンピユータに記憶さ
せていたリード12aや電極パツド14のパター
ンに基づいて、全てのリードや電極パツドを算出
し、これにより全てのリードと電極パツド位置を
認識して自動ワイヤボンダ22を作動させること
ができる。 When the semiconductor pellet 13 is fixed in the recess 11 of the printed circuit board 10, the position detection device 21, which is a combination of a TV camera 19 and a computer 20, is activated, as shown in FIG. This device 2
1 is an electrode pad 14 of a semiconductor pellet 13;
Two or more electrode pads 14a each selected from among the position recognition pads 17 of the printed circuit board 10
(Fig. 3) and the position of the position recognition pad 17, and when the position of each of these pads 14a, 17 is detected, the semiconductor pellet 1 is detected.
3 and the printed circuit board 10 can be detected. After detecting the relative positional relationship between the two, all the leads and electrode pads are calculated based on the patterns of the leads 12a and electrode pads 14 that have been stored in the computer in advance. The automatic wire bonder 22 can be activated by recognizing the position.
即ち、プリント回路基板10に形成した位置認
識パツド17を利用することにより、半導体ペレ
ツトの電極パツド14の位置を自動的に認識する
のと全く同様にしてプリント回路基板10の位
置、換言すればリード12aの位置を自動的に認
識することができるのである。このため、ボンデ
イングの最初に作業者がプリント回路基板を目視
にて位置合せする必要はなくなり、ボンデイング
の全自動化を実現することができるのである。 That is, by using the position recognition pads 17 formed on the printed circuit board 10, the position of the printed circuit board 10, in other words, the leads can be determined in exactly the same way as the position of the electrode pad 14 of the semiconductor pellet is automatically recognized. 12a can be automatically recognized. Therefore, there is no need for an operator to visually align the printed circuit board at the beginning of bonding, making it possible to fully automate bonding.
以上のように本発明の半導体のプリント回路基
板はその表面の少なくとも2箇所に位置認識用の
パツドを形成する一方、本発明のワイヤボンデイ
ング方法では、この位置認識用パツドを利用して
リード位置を検出し、半導体ペレツトの電極パツ
ドの位置認識と全く同様にしてリード位置を認識
することができるので、自動ワイヤボンデイング
工程の初期の位置合せ作業をも自動的に行なうこ
とができ、これによつて全自動ワイヤボンデイン
グを実現することができるという大なる効果を奏
する。 As described above, the semiconductor printed circuit board of the present invention has position recognition pads formed on at least two locations on its surface, while the wire bonding method of the present invention uses these position recognition pads to identify lead positions. Since the lead position can be detected and recognized in exactly the same way as the position of the electrode pad of a semiconductor pellet, the initial positioning work of the automatic wire bonding process can be performed automatically. This has the great effect of realizing fully automatic wire bonding.
本発明によれば、半導体ペレツトとベースとの
相対位置関係を精度良く、自動的に、迅速に認識
できるので、ペレツト・ベース間のワイヤボンデ
イングの自動化が図れる等の効果がある。 According to the present invention, the relative positional relationship between the semiconductor pellet and the base can be recognized automatically and quickly with high precision, so that wire bonding between the pellet and the base can be automated.
第1図はプリント回路基板に半導体ペレツトを
実装した状態の斜視図、第2図はその要部拡大平
面図、第3図は本発明の要部を拡大して示す第2
図と同様の平面図、第4図はその断面図、第5図
は位置検出方法を示す側面図である。
10…プリント回路基板、11…凹所、12…
回路、12a…リード、13…半導体ペレツト、
14,14a…電極パツド、15…ワイヤ、17
…位置認識パツド、19…TVカメラ、20…コ
ンピユータ、21…位置検出装置、22…自動ワ
イヤボンダ。
Fig. 1 is a perspective view of a semiconductor pellet mounted on a printed circuit board, Fig. 2 is an enlarged plan view of the main part thereof, and Fig. 3 is an enlarged view of the main part of the present invention.
4 is a sectional view thereof, and FIG. 5 is a side view showing a position detection method. 10...Printed circuit board, 11...Recess, 12...
circuit, 12a... lead, 13... semiconductor pellet,
14, 14a... Electrode pad, 15... Wire, 17
...Position recognition pad, 19...TV camera, 20...Computer, 21...Position detection device, 22...Automatic wire bonder.
Claims (1)
導体ペレツトと、前記半導体ペレツトを固定する
ためのベースと、前記ベース上に設けられたワイ
ヤボンデイング部を有し、前記半導体ペレツトと
前記ワイヤボンデイング部間にワイヤボンデイン
グを施すようにした半導体装置において、前記ベ
ースに固定された前記半導体ペレツトの第一の角
部近傍であつて前記ベース上に光学的に認識可能
な第一の位置認識用パツドを設け、前記半導体ペ
レツトの第二の角部近傍であつて前記ベースに光
学的に認識可能な第二の位置認識用パツドを設け
たことを特徴とする半導体装置。 2 前記第二の角部は前記第一の角部に対向する
角部であることを特徴とする特許請求の範囲第1
項記載の半導体装置。[Scope of Claims] 1. A semiconductor pellet having an electrode pad and having a rectangular planar shape, a base for fixing the semiconductor pellet, and a wire bonding part provided on the base, In a semiconductor device in which wire bonding is performed between the semiconductor pellet and the wire bonding portion, there is a first optically recognizable first corner on the base near the first corner of the semiconductor pellet fixed to the base. 1. A semiconductor device comprising: a position recognition pad, the second position recognition pad being provided near a second corner of the semiconductor pellet and being optically recognizable on the base. 2. Claim 1, wherein the second corner is a corner opposite to the first corner.
1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249680A JPS56110244A (en) | 1980-02-06 | 1980-02-06 | Printed circuit board for semiconductor device and wire bonding method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249680A JPS56110244A (en) | 1980-02-06 | 1980-02-06 | Printed circuit board for semiconductor device and wire bonding method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56110244A JPS56110244A (en) | 1981-09-01 |
| JPS6337498B2 true JPS6337498B2 (en) | 1988-07-26 |
Family
ID=11806975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1249680A Granted JPS56110244A (en) | 1980-02-06 | 1980-02-06 | Printed circuit board for semiconductor device and wire bonding method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56110244A (en) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50140858A (en) * | 1974-05-02 | 1975-11-12 | ||
| JPS5310426B2 (en) * | 1974-10-04 | 1978-04-13 | ||
| JPS5141960A (en) * | 1974-10-07 | 1976-04-08 | Shinkawa Seisakusho Kk | Handotaino waiyabondeinguhoho |
| JPS5237768A (en) * | 1975-09-19 | 1977-03-23 | Seiko Instr & Electronics Ltd | Substrate having positioning marks |
| JPS52127069A (en) * | 1976-04-16 | 1977-10-25 | Shinkawa Ltd | Wire bonding apparatus |
| JPS5329068A (en) * | 1976-08-31 | 1978-03-17 | Sony Corp | Automatic wire bonding unit |
| JPS5390863A (en) * | 1977-01-21 | 1978-08-10 | Hitachi Ltd | Wire bonding method and mark provided on subsutrate |
| JPS5826664B2 (en) * | 1977-09-27 | 1983-06-04 | 松下電器産業株式会社 | automatic wire bonding method |
| JPS5847704Y2 (en) * | 1978-04-10 | 1983-10-31 | 日本電気株式会社 | Container for semiconductor devices |
| JPS5827657B2 (en) * | 1978-04-12 | 1983-06-10 | 株式会社日立製作所 | Tape carrier type bonding method and device |
| JPS5629357A (en) * | 1979-08-18 | 1981-03-24 | Mitsubishi Electric Corp | Semiconductor container |
| JPS5737768A (en) * | 1980-08-18 | 1982-03-02 | Pioneer Electronic Corp | Bookshelf type record player |
-
1980
- 1980-02-06 JP JP1249680A patent/JPS56110244A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56110244A (en) | 1981-09-01 |
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