JPS6341987B2 - - Google Patents

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Publication number
JPS6341987B2
JPS6341987B2 JP10952785A JP10952785A JPS6341987B2 JP S6341987 B2 JPS6341987 B2 JP S6341987B2 JP 10952785 A JP10952785 A JP 10952785A JP 10952785 A JP10952785 A JP 10952785A JP S6341987 B2 JPS6341987 B2 JP S6341987B2
Authority
JP
Japan
Prior art keywords
etching
dry etching
polycrystalline silicon
silicon film
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10952785A
Other languages
Japanese (ja)
Other versions
JPS61266584A (en
Inventor
Hiroyuki Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokuda Seisakusho Co Ltd
Original Assignee
Tokuda Seisakusho Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokuda Seisakusho Co Ltd filed Critical Tokuda Seisakusho Co Ltd
Priority to JP10952785A priority Critical patent/JPS61266584A/en
Publication of JPS61266584A publication Critical patent/JPS61266584A/en
Publication of JPS6341987B2 publication Critical patent/JPS6341987B2/ja
Granted legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、ドライエツチング方法に関し、特に
半導体基板上に堆積されたシリコン窒化膜や多結
晶シリコン膜等をケミカルドライエツチングする
方法の改良に係わる。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dry etching method, and particularly to an improvement in a method for chemically dry etching a silicon nitride film, a polycrystalline silicon film, etc. deposited on a semiconductor substrate.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体集積回路の製造においては、シリコン等
の半導体基板上に各種の膜を堆積した後、写真蝕
刻法により形成されたレジストパターン等をマス
クとして該膜を選択的にエツチングする工程が行
われている。かかる工程でのエツチング方法とし
ては、従来よりウエツトエツチング法が採用され
ているが、危険な作業を伴うばかりか、エツチン
グ液の廃棄による公害の発生等の問題があつた。
In the manufacture of semiconductor integrated circuits, a process is performed in which various films are deposited on a semiconductor substrate such as silicon, and then the films are selectively etched using a resist pattern formed by photolithography as a mask. . As an etching method in this process, a wet etching method has conventionally been adopted, but it not only involves dangerous work but also poses problems such as the generation of pollution due to the disposal of the etching solution.

このようなことから、最近、ガス反応を利用し
たドライエツチング方法に移行しつつある。ドラ
イエツチング方法には、各種の方法が知られてい
るが、中でもケミカルドライエツチング法
(CDE法)は等方的形状で高い選択性を有する。
このCDE法は、マイクロ波プラズマにより反応
性ガスを励起し、生成した活性種をプラズマ室と
分離された反応室に輸送し、該反応室内の被エツ
チング材と反応せしめてエツチングするものであ
る。
For these reasons, there has recently been a shift toward dry etching methods that utilize gas reactions. Various dry etching methods are known, among which the chemical dry etching method (CDE method) has high selectivity in isotropic shapes.
This CDE method excites a reactive gas with microwave plasma, transports the generated active species to a reaction chamber separated from the plasma chamber, and reacts with the material to be etched in the reaction chamber to perform etching.

しかしながら、上述したCDE法により複数枚
の被エツチング材(例えば大口径のウエハ)を限
られた容積の反応室内で一度に処理しようとする
と、ウエハ位置が制約され、特にウエハ面内での
エツチングの均一性が悪化するという問題があつ
た。。この主な原因は、エツチング面積が増大す
ると、ローデイング効果等によりエツチング反応
が供給律速的になり、ウエハ周辺で活性種が消費
され、ウエハ中心部までその活性種が達しないこ
とによるものである。
However, when attempting to process multiple materials to be etched (for example, large-diameter wafers) at once in a reaction chamber with a limited volume using the above-mentioned CDE method, the wafer position is restricted, and in particular, the etching process within the wafer plane is limited. There was a problem that uniformity deteriorated. . The main reason for this is that as the etching area increases, the etching reaction becomes rate-limiting due to the loading effect, and active species are consumed around the wafer and do not reach the center of the wafer.

〔発明の目的〕[Purpose of the invention]

本発明は、被エツチング材の面内並びに被エツ
チング材間でのエツチングの均一性を向上したド
ライエツチング方法を提供しようとするものであ
る。
The present invention aims to provide a dry etching method that improves the uniformity of etching within the surface of a material to be etched as well as between materials to be etched.

〔発明の概要〕 本発明は、マイクロ波プラズマによつて反応性
ガスを励起し、生成した活性種をプラズマ室と分
離した反応室に輸送し、被エツチング材と反応せ
しめてドライエツチングを行なう方法において、
前記反応性ガスにHeを添加することを特徴とす
るものである。かかる本発明によれば、反応性ガ
スにHeを添加して、活性種を含むガスのトータ
ル流量を増大させることによつて、被エツチング
材の全面に亙つて活性種を均一に供給でき、ひい
ては均一なエツチングを遂行できる。
[Summary of the Invention] The present invention is a dry etching method in which a reactive gas is excited by microwave plasma, the generated active species are transported to a reaction chamber separated from a plasma chamber, and reacted with a material to be etched. In,
The method is characterized in that He is added to the reactive gas. According to the present invention, by adding He to the reactive gas and increasing the total flow rate of the gas containing active species, the active species can be uniformly supplied over the entire surface of the material to be etched, and as a result, Able to perform uniform etching.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面を参照して詳細に
説明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は、本実施例のCDEに使用されるエツ
チング装置の断面図、第2図は第1図の真空チヤ
ンバ内に装填されるカセツトの要部断面図であ
る。図中の1は、真空チヤンバであり、このチヤ
ンバ1の中心には該チヤンバ1の下面から貫通さ
れたシヤフト2に軸着された支持台2が回転可能
に配置されている。前記シヤフト2のチヤンバ1
の外に位置する部分には軸受4が設けられ、かつ
該シヤフト2の下端はモータ5の駆動軸6とベル
ト7を介して枢着されている。また、前記支持台
3上には第2図に示すカセツト8が載置される。
このカセツト8は、一側面が開口され三側面に支
持板を有し、かつ各支持板の内側面には複数の溝
9が上下方向に形成されている。これら溝9に
は、一段置きにアルミニウム製の遮蔽板10が設
置されている。前記チヤンバ1の左側壁には活性
種を含むガスを導入するガス導入管11が、同チ
ヤンバ1の右側壁にはガス排出管12が夫々設け
られている。これらガス導入管11及び排気管1
2のチヤンバ1の入口付近には、夫々多数のスリ
ツトを有する第1のの分散板13,13が配設さ
れている。また、前記ガス導入管11と前記支持
台3との間、及び前記排気管12と支持台3との
間には、夫々多数のスリツトを有する第2の分散
板14,14が配設されている。
FIG. 1 is a sectional view of an etching apparatus used in the CDE of this embodiment, and FIG. 2 is a sectional view of a main part of a cassette loaded into the vacuum chamber of FIG. 1. Reference numeral 1 in the figure indicates a vacuum chamber, and a support base 2 is rotatably disposed at the center of the chamber 1, which is pivotally attached to a shaft 2 that penetrates from the bottom surface of the chamber 1. Chamber 1 of the shaft 2
A bearing 4 is provided at a portion located outside the shaft 2, and the lower end of the shaft 2 is pivotally connected to a drive shaft 6 of a motor 5 via a belt 7. Further, a cassette 8 shown in FIG. 2 is placed on the support stand 3.
The cassette 8 has an open side on one side and support plates on three sides, and a plurality of grooves 9 are formed in the vertical direction on the inner side of each support plate. In these grooves 9, aluminum shielding plates 10 are installed every other row. A gas introduction pipe 11 for introducing a gas containing active species is provided on the left side wall of the chamber 1, and a gas exhaust pipe 12 is provided on the right side wall of the chamber 1. These gas introduction pipe 11 and exhaust pipe 1
Near the entrance of the second chamber 1, first dispersion plates 13, 13 each having a large number of slits are arranged. Further, second dispersion plates 14, 14 each having a large number of slits are disposed between the gas introduction pipe 11 and the support stand 3, and between the exhaust pipe 12 and the support stand 3. There is.

次に、前述した第1図及び第2図図示の装置を
用いてウエハ上の多結晶シリコン膜をドライエツ
チングを説明する。
Next, dry etching of a polycrystalline silicon film on a wafer using the apparatus shown in FIGS. 1 and 2 will be described.

まず、直径6インチの単結晶シリコンウエハ2
1を熱酸化処理して厚さ約200Åのシリコン酸化
膜22を形成し、更にCVD法により該酸化膜2
2上に厚さ約4000Åの不純物無添加の多結晶シリ
コン膜23を堆積した後、写真蝕刻法により該多
結晶シリコン膜23上にレジストパターン24を
形成した(第3図図示)。
First, a single crystal silicon wafer 2 with a diameter of 6 inches
1 is thermally oxidized to form a silicon oxide film 22 with a thickness of about 200 Å, and then the oxide film 2 is further removed by CVD.
After depositing an impurity-free polycrystalline silicon film 23 with a thickness of about 4000 Å on the polycrystalline silicon film 23, a resist pattern 24 was formed on the polycrystalline silicon film 23 by photolithography (as shown in FIG. 3).

次いで、第3図図示のウエハ21を第2図に示
すようにカセツト8の遮蔽板10間の溝9に25枚
水平に挿入設置した後、該カセツト8をチヤンバ
1の支持台3上に設置した。つづいて、図示しな
いプラズマ室にCF4、O2及びN2を夫々100sccm、
50sccm、50sccmの条件で供給すると共に、He
を該CF4、O2に対して所定の比率で供給し、
2.45GHzのマイクロ波より該ガス励起した。ひき
つづき、排気管12によつて圧力を20Paとした
真空チヤンバ1内に前記Heで希釈された活性種
をガス導入管11を通して導入すると共に、モー
タ5により支持台3上のカセツト8をゆつくり回
転させて、カセツト8に設置した複数枚のウエハ
21上の露出した多結晶シリコン膜23をケミカ
ルドライエツチングを行なつた。
Next, 25 wafers 21 shown in FIG. 3 are inserted horizontally into the groove 9 between the shielding plates 10 of the cassette 8 as shown in FIG. did. Next, CF 4 , O 2 and N 2 were added at 100 sccm each into a plasma chamber (not shown).
In addition to supplying He under conditions of 50sccm and 50sccm,
is supplied at a predetermined ratio to the CF 4 and O 2 ,
The gas was excited by 2.45 GHz microwave. Subsequently, the active species diluted with He is introduced into the vacuum chamber 1 at a pressure of 20 Pa through the gas introduction pipe 11 through the exhaust pipe 12, and the cassette 8 on the support base 3 is slowly rotated by the motor 5. Then, the exposed polycrystalline silicon film 23 on the plurality of wafers 21 placed in the cassette 8 was subjected to chemical dry etching.

しかして、上記実施例によりケミカルドライエ
ツチングした後、カセツト8を真空チヤンバ1か
ら取出し、該カセツト8に設置した25枚のウエハ
21を取出して前記エツチング時におけるHe/
(CF4+O2)で示すHe添加量に対する多結晶シリ
コン膜のエツチングの均一性を調べたところ、第
4図のAに示す特性線を得た。なお、エツチング
の均一性はカセツト8から取出した25枚のウエハ
でのエツチングの最大値(Max)と最少値
(Min)を求め、[(Max−Min)/(Max+
Min)]×100(%)から算出した。また、Heの添
加量に対する多結晶シリコン膜のエツチングレー
トを調べたところ、第5図のAに示す特性線を得
た。第4図から明らかなように、Heを100%以上
添加した活性種によりケミカルドライエツチング
を行なうことにより、ウエハの面内及びウエハ間
のエツチング均一性を向上できることが分る。一
方、Heの添加量の上限については、第5図に示
すようにHeの添加量の増大に伴つてエツチング
レート250Å/min以下となることから、そのHe
添加量を400%以下にすることが望ましい。
After the chemical dry etching according to the above embodiment, the cassette 8 was taken out from the vacuum chamber 1, the 25 wafers 21 placed in the cassette 8 were taken out, and the He
When the uniformity of etching of the polycrystalline silicon film was investigated with respect to the amount of He added (CF 4 +O 2 ), a characteristic line shown at A in FIG. 4 was obtained. The uniformity of etching is determined by determining the maximum value (Max) and minimum value (Min) of etching on 25 wafers taken out from cassette 8, and calculating the etching uniformity by [(Max-Min)/(Max+
Min)] × 100 (%). Further, when the etching rate of the polycrystalline silicon film was investigated with respect to the amount of He added, a characteristic line shown at A in FIG. 5 was obtained. As is clear from FIG. 4, etching uniformity within the wafer surface and between wafers can be improved by performing chemical dry etching using active species containing 100% or more He. On the other hand, regarding the upper limit of the amount of He added, as shown in Figure 5, as the amount of He added increases, the etching rate becomes less than 250 Å/min.
It is desirable that the amount added be 400% or less.

また、不純物無添加の多結晶シリコン膜の代わ
りに不純物(例えばリン)を添加した多結晶シリ
コン膜について、実施例と同様な条件でケミカル
ドライエツチングを行なつてHe添加量に対する
リン添加多結晶シリコン膜のエツチングの均一
性、並びにHeの添加量に対するリン添加多結晶
シリコン膜のエツチングレートを調べたところ、
第4図のB及び第5図のBに示す特性線を得た。
これら第4図及び第5図より、不純物添加多結晶
シリコン膜を被エツチング材とした場合には、エ
ツチングの均一性の点から、Heの下限値を250
%、エツチングレートの点から、その上限値を
400%とすることが望ましいことが分る。
In addition, chemical dry etching was performed on a polycrystalline silicon film doped with an impurity (for example, phosphorus) instead of a polycrystalline silicon film with no impurity added, under the same conditions as in the example. When we investigated the etching uniformity of the film and the etching rate of the phosphorus-doped polycrystalline silicon film with respect to the amount of He added, we found that:
Characteristic lines shown in B in FIG. 4 and B in FIG. 5 were obtained.
From these Figures 4 and 5, when an impurity-doped polycrystalline silicon film is used as the material to be etched, the lower limit of He is set to 250 from the viewpoint of uniformity of etching.
%, and its upper limit from the etching rate point of view.
It turns out that it is desirable to set it to 400%.

上記実施例に示すように複数枚のウエハ21を
カセツト8に設置してエツチングを行なう際、そ
れらウエハ21間にアルミニウム製の遮蔽板10
を配置することにより、ウエハ21から放射され
る赤外線による輻射熱によつて上下に隣接するウ
エハ21が相互に加熱されるのを阻止し、該ウエ
ハの温度上昇に伴うエツチングの不均一化を防止
できる。その結果、複数枚のウエハを一度にエツ
チングできるため、生産性を著しく向上できる。
As shown in the above embodiment, when etching is performed with a plurality of wafers 21 placed in the cassette 8, an aluminum shielding plate 10 is placed between the wafers 21.
By arranging the wafers 21, it is possible to prevent vertically adjacent wafers 21 from being mutually heated by the radiant heat of infrared rays emitted from the wafers 21, and to prevent non-uniform etching due to an increase in the temperature of the wafers. . As a result, a plurality of wafers can be etched at once, resulting in a marked improvement in productivity.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く、本発明によれば反応性ガス
にHeを添加して、活性種を含むガスのトータル
流量を増大させることによつて、被エツチング材
の全面に亙つて活性種を均一に供給でき、ひいて
はエツチングの均一性を達成し得るドライエツチ
ング方法を提供できるものである。
As detailed above, according to the present invention, by adding He to the reactive gas and increasing the total flow rate of the gas containing active species, the active species can be distributed uniformly over the entire surface of the material to be etched. Therefore, it is possible to provide a dry etching method that can provide a uniform etching process and achieve etching uniformity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例で使用したエツチング
装置の一形態を示す断面図、第2図は第1図の真
空チヤンバ内に装填されるカセツトの要部断面
図、第3図は本実施例で用いるウエハの状態を示
す断面図、第4図はHeの添加量に対する不純物
無添加の多結晶シリコン膜及び不純物添加多結晶
シリコン膜のエツチングの均一性を示す特性図、
第5図はHeの添加量に対する不純物無添加多結
晶シリコン膜及び不純物添加多結晶シリコン膜の
エツチングレートを示す特性図である。 1…真空チヤンバ、3…支持台、5…モータ、
8…カセツト、10…アルミニウム製の遮蔽板、
11…ガス導入管、12…排気管、21…ウエ
ハ、22…シリコン酸化膜、23…不純物無添加
多結晶シリコン膜、24…レジストパターン。
FIG. 1 is a cross-sectional view showing one form of etching apparatus used in an embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part of a cassette loaded into the vacuum chamber of FIG. 1, and FIG. 4 is a cross-sectional view showing the state of a wafer used in the example; FIG. 4 is a characteristic diagram showing the etching uniformity of an impurity-free polycrystalline silicon film and an impurity-doped polycrystalline silicon film with respect to the amount of He added;
FIG. 5 is a characteristic diagram showing the etching rate of an impurity-free polycrystalline silicon film and an impurity-doped polycrystalline silicon film with respect to the amount of He added. 1... Vacuum chamber, 3... Support stand, 5... Motor,
8...Cassette, 10...Aluminum shielding plate,
DESCRIPTION OF SYMBOLS 11... Gas introduction pipe, 12... Exhaust pipe, 21... Wafer, 22... Silicon oxide film, 23... Impurity-free polycrystalline silicon film, 24... Resist pattern.

Claims (1)

【特許請求の範囲】 1 マイクロ波プラズマによつて反応性ガスを励
起し、生成した活性種をプラズマ室と分離した反
応室に輸送し、被エツチング材と反応せしめてド
ライエツチングを行なう方法において、前記反応
性ガスにHeを添加することを特徴とするドライ
エツチング方法。 2 反応性ガスとしてCF4とO2の混合ガス又は
CF4とO2とN2の混合ガスを使用することを特徴
とする特許請求の範囲第1項記載のドライエツチ
ング方法。 3 被エツチング材がウエハであり、かつ複数枚
のウエハを反応室内に多段に配置した状態でドラ
イエツチングを行なうことを特徴とする特許請求
の範囲第1項記載のドライエツチング方法。
[Scope of Claims] 1. A method of dry etching by exciting a reactive gas with microwave plasma, transporting the generated active species to a reaction chamber separate from the plasma chamber, and reacting with the material to be etched, A dry etching method characterized in that He is added to the reactive gas. 2 Mixed gas of CF 4 and O 2 as reactive gas or
The dry etching method according to claim 1, characterized in that a mixed gas of CF 4 , O 2 and N 2 is used. 3. The dry etching method according to claim 1, wherein the material to be etched is a wafer, and the dry etching is performed with a plurality of wafers arranged in multiple stages in a reaction chamber.
JP10952785A 1985-05-22 1985-05-22 Dry etching method Granted JPS61266584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10952785A JPS61266584A (en) 1985-05-22 1985-05-22 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10952785A JPS61266584A (en) 1985-05-22 1985-05-22 Dry etching method

Publications (2)

Publication Number Publication Date
JPS61266584A JPS61266584A (en) 1986-11-26
JPS6341987B2 true JPS6341987B2 (en) 1988-08-19

Family

ID=14512517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10952785A Granted JPS61266584A (en) 1985-05-22 1985-05-22 Dry etching method

Country Status (1)

Country Link
JP (1) JPS61266584A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0244989A (en) * 1988-08-05 1990-02-14 Matsushita Electric Ind Co Ltd Digital convergence device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697676B2 (en) * 1985-11-26 1994-11-30 忠弘 大見 Wafer susceptor device
US5201994A (en) * 1988-11-18 1993-04-13 Kabushiki Kaisha Tokuda Seisakusho Dry etching method
JPH08186095A (en) * 1994-12-28 1996-07-16 Kawasaki Steel Corp Contact hole forming method and etching apparatus
KR100869359B1 (en) * 2006-09-28 2008-11-19 주식회사 하이닉스반도체 Method of manufacturing recess gate of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0244989A (en) * 1988-08-05 1990-02-14 Matsushita Electric Ind Co Ltd Digital convergence device

Also Published As

Publication number Publication date
JPS61266584A (en) 1986-11-26

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