JPS6343201U

JPS6343201U -

Info

Publication number: JPS6343201U
Application number: JP1986137415U
Authority: JP
Priority date: 1986-09-08
Filing date: 1986-09-08
Publication date: 1988-03-23

Description

[Brief explanation of the drawing]

図は本考案の一実施例を示した構成図である。１は突き合せ部、２は増巾器、３は第１のコン
パレータ、４は第２のコンパレータ、５はアツプ
ダウンカウンタ、６は発振部、７はデイジタル―
アナログ変換器。 The figure is a configuration diagram showing an embodiment of the present invention. 1 is a matching section, 2 is an amplifier, 3 is a first comparator, 4 is a second comparator, 5 is an up/down counter, 6 is an oscillation section, and 7 is a digital circuit.
analog converter.

Claims

[Scope of utility model registration request]

A reference value for the dead band width is set on the positive side of the input,
The first comparator outputs an up signal when the input signal is greater than this reference value, and a reference value for the dead band width is set on the negative side of the input, and outputs a down signal when the input signal is greater than this reference value. A second comparator, an up-down counter to which the up and down signals are input to up and down terminals, respectively, and a clock signal is input to the clock terminal, and a digital output of this up-down counter is input. and a digital-to-analog converter for converting the digital signal into an analog signal, the deviation between the current output of the digital-to-analog converter and the setting signal is determined, and this deviation signal is applied to each input of the first and second comparators. A dead band setting circuit characterized in that it is configured to output to a terminal.