JPS6344265U - - Google Patents
Info
- Publication number
- JPS6344265U JPS6344265U JP13615986U JP13615986U JPS6344265U JP S6344265 U JPS6344265 U JP S6344265U JP 13615986 U JP13615986 U JP 13615986U JP 13615986 U JP13615986 U JP 13615986U JP S6344265 U JPS6344265 U JP S6344265U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- gate signal
- write gate
- recording device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Digital Magnetic Recording (AREA)
Description
第１図はこの考案の一実施例による磁気記録装
置のブロツク図、第２図は第１図の動作タイムチ
ヤート、第３図は従来の磁気記録装置のブロツク
図、第４図は第３図のタイムチヤートを示す。
２は磁気記録装置、７はライトゲート線、８は
外来ノイズ、９は第１フリツプフロツプＦＦ１、
１０はデレイ回路、１１はＡＮＤ回路、１２は第
２フリツプフロツプＦＦ２．なお図中、同一符号
は、同一又は相当部分を示す。
FIG. 1 is a block diagram of a magnetic recording device according to an embodiment of this invention, FIG. 2 is an operation time chart of FIG. 1, FIG. 3 is a block diagram of a conventional magnetic recording device, and FIG. 4 is a diagram of FIG. Shows the time chart. 2 is a magnetic recording device, 7 is a write gate line, 8 is an external noise, 9 is a first flip-flop FF1,
10 is a delay circuit, 11 is an AND circuit, 12 is a second flip-flop FF2. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
終了を制御するデータ記録装置で、ライトゲート
信号がオフしたらセツトされる第１のフリツプフ
ロツプと、このフリツプフロツプを一定時間後に
自己リセツトさせるためのデレイ回路と、第１の
フリツプフロツプがセツトされている期間中に、
ライトゲート信号が再オンしたらセツトされ信号
を出力する第２のフリツプフロツプとを持つこと
を特徴とするデータ記録装置。 Start recording data by write gate signal.
A data recording device that controls termination includes a first flip-flop that is set when the write gate signal is turned off, a delay circuit that causes the flip-flop to self-reset after a certain period of time, and a delay circuit that resets the flip-flop after a certain period of time, while the first flip-flop is set. To,
A data recording device comprising a second flip-flop which is set and outputs a signal when the write gate signal is turned on again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13615986U JPS6344265U (en) | 1986-09-05 | 1986-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13615986U JPS6344265U (en) | 1986-09-05 | 1986-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6344265U true JPS6344265U (en) | 1988-03-24 |
Family
ID=31039018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13615986U Pending JPS6344265U (en) | 1986-09-05 | 1986-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6344265U (en) |
-
1986
- 1986-09-05 JP JP13615986U patent/JPS6344265U/ja active Pending
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