JPS6347032B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential absolute value circuit that obtains a unipolar output based on the difference between two inputs.

When instructing the white balance adjustment of a color television camera using a unidirectional indicator that is not a zero-center type, it is necessary to drive the indicator with a unipolar output that corresponds to the difference between the two inputs. Conventionally, a circuit shown in FIG. 1 has been used.

That is, in the circuit diagram of the same figure, the voltages V ₁ ,
V ₂ is applied to the input terminals 1 and 2 of the differential amplifier A ₁ , the difference between the voltages V ₁ and V ₂ is determined, and the inverting voltage is applied to the resistors R ₁ to R ₇ , the diodes D ₁ and D ₂ and the operational amplifier, etc. It is applied to a known absolute value circuit consisting of amplifiers A ₂ and A ₃ , and no matter whether the polarity of the difference output of differential amplifier A ₁ is positive or negative, an absolute value output OUT with a specific polarity is obtained from output terminal 3. There is.

The absolute value circuit exhibits the limiting characteristics shown in Figure 2 due to the addition of resistors R ₆ and R ₇ and the bias voltage -V, and when the difference between voltages V ₁ and V ₂ exceeds a predetermined value, The output current _I0 is kept constant.

However, in the configuration of FIG. 1, the amplifier A ₁
~ A ₃ is required, which increases the number of parts and power consumption current, and changes in the limiting characteristics cause the second
The current change characteristics near the zero point shown in the figure fluctuate, resulting in drawbacks such as the inability to accurately indicate the zero point.

The present invention aims to eliminate all of these conventional drawbacks at once, and provides a differential absolute value circuit that can obtain differential absolute value outputs with a simple configuration.

The details of the present invention will be explained below with reference to the circuit diagram of FIG. 3 showing an embodiment.

In the figure, a differential circuit is configured by transistors Q ₁ and Q ₂ as the first and second transistors, a transistor Q ₃ given a base bias Eb, and resistors R ₁₁ to _{R 13} . ,
Voltages V ₁ and V ₂ are applied as two inputs to the bases of transistors Q ₁ and Q ₂ via input terminals 1 and 2.

In addition, a transistor as a third transistor
Q ₄ has its collector and base connected to the collector of transistor Q ₁ , and
An emitter is connected to the collector of Q ₂ via a resistor R ₁₄ , and a transistor Q ₅ as a fourth transistor has its collector and base connected to the collector of transistor Q ₂ , and
The emitter of the transistor Q ₁ is connected to the collector of the transistor Q 1 via a resistor R ₁₅ , and the emitter of Q ₆ as the fifth transistor is connected to the collector of the transistor Q ₂ via a resistor R ₁₆ . , whose base is connected to the base of transistor Q ₄ and whose collector is connected to output terminal 3, and transistor Q ₇ as the sixth transistor.
is connected to the collector of transistor Q ₁ through resistor R ₁₇ , and the base is connected to transistor Q ₅
The collector is connected to the output terminal 3.

In addition, transistors Q ₈ to Q ₁₀ and resistor R ₁₈
A constant current circuit composed of ~ _R20 is inserted between the power supply _Vcc and the transistors _Q1 ~ _Q7 ,
This allows current to be supplied to the collectors of transistors Q ₁ and Q ₂ respectively.

Therefore, collector currents I _c1 and I _c2 corresponding to the difference between the voltages V ₁ and V ₂ flow to the collectors of the transistors Q ₁ and Q ₂ , and a current equal to the difference between the collector currents I _c1 and I _c2 flows through the transistor Q _4. or _Q5 , the collector current _Ic6 or _Ic7 , which is inversely proportional to the respective resistance values of resistors _R14 and _R16 or _R15 and _R17 , flows into the transistor
leads to Q ₆ or Q ₇ and this collector current I _c6 or
Since I _c7 corresponds to the difference between collector currents I _c1 and I _c2 , if collector current I _c1 is larger than I c2, collector current I _c6 will flow, while collector current _{I c2 will} be smaller than I _c1 . If it is greater than the collector current I _c7
Therefore, no matter which of the voltages V ₁ and V ₂ is large, a current corresponding to the difference passes from the output terminal 3 to the load such as the indicator M, and its polarity is always constant.

Here, the base-emitter voltages of transistors Q ₁ and Q ₂ are V _BE1 , V _BE2 , and the voltages between the bases and emitters of transistors Q ₁ and Q _{2 are}
When the DC current amplification factor H _FE is set to infinity, V ₁ −V _BE1 −I _C1・R ₁₁ =V ₂ −V _BE2 −I _C2・R ₁₂ Now, V _BE1 = V _BE2 , R ₁₁ = R ₁₂ =R, then I _C1 −I _C2 =(V ₁ −V ₂ )/R (1) is obtained.

Therefore, if V ₁ > V ₂ in equation (1), then I _C1 > I _C2 , and when R ₁₉ = R ₂₀ , I _C1
- If the current of I _C2 passes from the emitter to the collector of transistor Q ₄ and R ₁₄ = R ₁₆ , a collector current I _C6 having a value equal to the collector current I _C4 of transistor Q ₄ also passes to transistor _{Q 6} .

Note that at this time, since the transistor _Q5 is reverse biased, the collector current I _C5 is in a cut-off state, and _{the collector current I C7 does} not flow through the transistor Q7 either.

Also, if V ₁ < V ₂ in equation (1), then I _C1 < I _C2
Then, the current of I _C2 −I _C1 passes to transistor Q ₅ ,
If R ₁₅ =R ₁₇ , a collector current I _C7 having a value equal to the collector current I _C5 of transistor Q ₅ passes through transistor Q ₇ .

Note that at this time, since transistor _Q4 is reverse biased, collector currents I _C4 and I _C6 do not flow.

As described above, a current proportional to V ₁ - V ₂ is taken out from the output terminal 3, and V ₁ > V ₂ or V ₁ < V ₂
In either case, the current from the output terminal 3 has the same polarity, and if the current flowing through the output terminal 3 is I ₀ and the coefficient determined according to the constant of each part is K, the following equation can be obtained.

I _O = K | V ₁ − V ₂ | ...(2) In addition, resistor R ₁₈ is connected to transistors Q ₉ and Q ₁₀
Transistor Q ₃ also operates as a constant current circuit, but these constant current circuits may be replaced with only resistors, and resistors R ₁₄ to
_R17 is not necessarily needed and each transistor
Various modifications are possible, such as the polarity of Q ₁ to _{Q 10} may be reversed depending on the conditions. FIG. 4 shows another embodiment composed of transistors Q' ₁ to Q' ₁₀ of opposite polarity, but since the operation is similar to that of the circuit shown in FIG. 3, a description thereof will be omitted.

Therefore, with the configurations shown in Figures 3 and 4, input/output characteristics similar to those shown in Figure 2 can be obtained, and since an output with a unipolar difference between two inputs is required, differential input It can be used when driving a unidirectional indicating instrument or when converting a differential input into a unipolar signal, and the differential output of transistors Q ₁ and Q ₂ can be used as an output current I. _O , stable zero output can be obtained when V ₁ = V ₂ .

As is clear from the above explanation, according to the present invention, a differential absolute value circuit with stable operation can be obtained with a simple configuration, and because the number of parts and power consumption current are small, it exhibits great effects in various electronic devices. .

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional example, Fig. 2 is a diagram showing input/output characteristics, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a circuit diagram showing another embodiment of the present invention. It is a diagram. Q ₁ , Q′ ₁ ~ Q ₁₀ , Q′ ₁₀ : Transistor, R ₁₁ ~
R ₂₀ : Resistor, 1, 2: Input terminal, 3: Output terminal.

Claims (1)

[Claims] 1 A first and a second transistor forming a differential circuit, a collector and a base connected to the collector of the first transistor, and an emitter connected to the collector of the second transistor via a resistor as necessary. a third transistor, a fourth transistor whose collector and base are connected to the collector of the second transistor, and whose emitter is connected to the collector of the first transistor via a resistor if necessary; A fifth transistor whose emitter is connected to the collector via a resistor as necessary, whose base is connected to the base of the third transistor, and whose collector is connected to the output terminal; The emitter is connected via a resistor and the base is connected to the fourth
A differential absolute value comprising a sixth transistor connected to the base of the transistor and whose collector is connected to the output terminal, and a constant current circuit that supplies current to each of the first and second transistors. circuit.