JPS6351606B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a superconducting timing signal forming circuit configured using Josephson junctions, which forms a rectangular wave timing signal with a steeper rise than a sinusoidal input signal.

Conventionally, as this kind of superconducting timing signal forming circuit, as shown in FIG. 1, a plurality of N (four in the figure) Josephson junctions J1, J2 having substantially equal separation current values I _S are used. ,... has a series circuit U in which JN are connected in series, and from one end side,
The input terminal T1 is led out through the resistor R0, while the other end of the series circuit U is connected to ground, and the output terminal T0 is derived from the midpoint of the connection between the series circuit U and the resistor R0.
A configuration has been proposed in which the following is derived.

According to the configuration of the superconducting timing signal forming circuit shown in FIG. 1, a sinusoidal input signal S as shown in FIG. 2A is generated between the input terminal T1 and the ground.
1, a sinusoidal current I1 (not shown) corresponding to the waveform of the input signal S1 flows through the resistor R0.
It flows to the series circuit U through the Therefore, if a current I1 having a larger amplitude than the critical current value I _S of the Josephson junctions J1 to JN is used as the input signal S1, the Josephson junctions J1 to JN of the series circuit U are , critical current value
If there is no variation in I _S , the value of current I1 will be the critical current value I _S in its positive and negative sections.
From the time points t1 and t1' when the superconducting state and -I _S are reached, the superconducting state simultaneously transitions to the voltage-carrying state, and therefore, each of the input signals S1 is In the positive and negative sections, a rectangular waveform voltage V0 (not shown) is obtained which rises sharply at times t1 and t1', respectively. As a result, a load is pre-loaded between the output terminal T0 and ground.
If RL is connected, the load RL receives a rectangular waveform signal that rises steeply at times t1 and t1' in each positive and negative section of the input signal S1, as shown in FIG. 2B. is obtained as the timing signal S2. In this case timing signal S2
is the Josephson junction J1 that constitutes the series circuit U.
The amplitude corresponds to the number N of ~JN.

Therefore, in the case of the conventional superconducting timing signal forming circuit shown in FIG. This is obtained by assuming that S2 has a desirable waveform.

However, it is extremely difficult to prepare the Josephson junctions J1, J2...JN that constitute the series circuit U without any variation in critical current value between them, and for this reason, the Josephson junctions J1...
If JN has variations in critical current value I _S between them, all Josephson junctions J1 to JN will not transition to the voltage state at the same time at the above-mentioned times t1 and t1', and Josephson junctions J1 to JN
However, the Josephson junction having a small critical current value gradually transitions to the voltage state, and as a result, the timing signal S2 rises in a stepwise manner as shown in FIG. 2C.

Therefore, the conventional superconducting timing signal forming circuit shown in FIG. 1 has the disadvantage that it is not possible to obtain the timing signal S2 with a desired waveform.

Therefore, the present invention aims to propose a novel superconducting timing signal forming circuit free from the above-mentioned drawbacks, which will become clear from the detailed description below.

FIG. 3 shows an embodiment of the superconducting timing signal forming circuit according to the first invention of the present application, in which a plurality of N (however, four in the figure) superconducting timing signal forming circuits each having approximately the same critical current value I _S A first series circuit U1 in which junctions J ₁ , J ₂ , ...J _N are connected in series, and a plurality of N Josephson junctions J ₁ ', J having substantially equal critical current values I _{' 2} '...J _N ' are connected in series.

Therefore, from one end side of the series circuits U1 and U2,
A common input terminal T is connected to the first resistor R1 and a Josephson junction (hereinafter simply referred to as a Josephson junction for simplicity) JS for generating a trigger signal.
1 has been derived.

Further, the other ends of the series circuits U1 and U2 are connected to ground.

Furthermore, a connection midpoint between the series circuit U1 and the resistor R1,
A resistor _R1 is connected between the series circuit U2 and the connection midpoint of Josephson junction JS, and the series circuit U
1 Josephson junction J _i and J _(i+1) (where i=1,
2...(N-1)) connection middle point and series circuit U2
A resistor R _(i+1) is connected between the connection midpoint of Josephson junctions J _i ′ and J′ _(i+1) .

Further, an output terminal T0 is led out from the connection midpoint between the series circuit U2 and Josephson junction JS.

The above is the configuration of the embodiment of the superconducting timing signal forming circuit according to the first invention of the present application. According to this configuration, the following operation can be obtained.

That is, if a sinusoidal input signal S1 as shown in FIG. 4A and similar to that described above in FIG. 2A is applied between the input terminal T1 and the ground, the input signal S
A sinusoidal current I1 (not shown) corresponding to the waveform of 1 flows into the series circuit U2 through the Josephson junction JS. Therefore, as the Josephson junction JS, one having a critical current value IJS that is slightly smaller than that of the Josephson junctions _J1 ' to _JN ' of the series circuit U2 is used in advance, and as the input signal S1, the Josephson junction _JS in terms of the current I1 is used. If a junction JS with an amplitude larger than the critical current value I _JS is used in advance, the value of the current I1 will be equal to the critical current value I _JS of the Josephson junction JS in each positive and negative section of the current I1. −I From the time t1 and t1′ when _JS is reached, Josephson junction
JS transitions from superconducting state to voltage charged state.

For this reason, as resistance R1, Josephson junction
If JS had a sufficiently smaller value than the internal resistance when it transitioned to the voltage state, the current I1 that had been flowing through the Josephson junction JS to the series circuit U2 would be In the positive and negative sections, almost no current flows from time t1 and t1', and instead, the current I2 rises from time t1 and t1' in each positive and negative section of the input signal S1. (not shown) flows to the series circuit U1 via the resistor R1. However, in this case,
The current I2 has a fourth addition to the current rising at times t1 and t1' in each positive and negative section of the input signal S1.
Trigger pulse-like current IT that rises sharply from time points t1 and t1' as shown by the solid line or dotted line in Figure B
This is obtained by superimposing the . As a result, the current I2 flows through the series circuit U as the resistor R1
If a _J -Josefson junction J ₁ -J _N of 1 is used in advance, _the critical current value _I Even if there is some variation in values, all Josephson junctions J ₁ to _J
At a time slightly later than 1', the superconducting state simultaneously transitions to the voltage-bearing state.

Also, Josephson junction J ₁ ~J _N of series circuit U1
transitions to the voltage state, the midpoint of the connection between the series circuit U1 and the resistor R1 becomes P ₁ , Josephson junction J _i and
When the connection midpoint of J _(i+1) is P _(i+1) , the connection midpoint P _k
(However, k=1, 2..., (i+1); Therefore, k=1,
2, _. Accordingly, in each of the positive and negative sections of the input signal S1, a current I _k that rises sharply from a time point slightly delayed from time points t1 and t1' is caused by a resistance R _k
via Josephson junction J _k of series circuit U2,
J _k+1 , ... flows to J _N. As a result, a current flows in the Josephson junctions J ₁ ′ to J _N ′ of the series circuit U2 as resistors R ₁ to R _N with a value sufficient to take on an amplitude larger than their critical current value I _S ′. If a J _- Josefson junction J ₁ ′ to J _N ′ having a sufficient value for All of _N ' simultaneously transition from the superconducting state to the voltage state at a time slightly delayed from time points t1 and t1' in each positive and negative section of the input signal S1.

Furthermore, the Josephson junction of the series circuit U2 is
If J ₁ ′ to J _N ′ transition to the voltage state, the output terminal T
Assuming that a load RL is connected between 0 and ground in advance, if the load RL is selected appropriately,
Between both ends of the series circuit U2, that is, between the output terminal T0 and ground, in each positive and negative section of the input signal S1,
From a time slightly later than time t1 and t1',
A steeply rising rectangular voltage V2 (not shown) is obtained, and in response, an input signal S1 is applied to the load RL as shown in FIG. 4C, similar to that described above in FIG. 2B. In the positive and negative intervals of , time t1 and t
A rectangular waveform signal that rises sharply from a time point slightly later than 1' is obtained as the timing signal S2. In this case, the timing signal S
2 is a Josephson junction that constitutes the series circuit U2.
The amplitude corresponds to the number N of J ₁ ′ to J _N ′.

Therefore, according to the superconducting timing signal forming circuit according to the first invention of the present application shown in FIG. 3, Josephson junctions J ₁ to J _N forming the series circuit U1 and Josephson junctions forming the series circuit U2
Even if J ₁ ′ to J _N ′ have some variation in critical current value between them, the rectangular wave timing signal S2 has a desirable waveform with a steep rise than the sinusoidal input signal S1. It has the great feature that it can be obtained as a commercial product.

Next, an example of a superconducting timing signal forming circuit according to the second invention of the present application will be described with reference to FIG. 5. Parts corresponding to those in FIG. Although omitted, the configuration described above in FIG. 3 has the same configuration as that in FIG. 3, except that the second resistor R2 is connected in parallel to the Josephson junction JS.

The above is an example of the configuration of the superconducting timing signal forming circuit according to the second invention of the present application.
Since it has the same configuration as the case shown in the figure, a detailed explanation thereof will be omitted, but as in the case of Fig. 3, a sinusoidal input signal S1 as shown in Fig. 4A is connected between the input terminal T1 and the ground. If applied, it is possible to obtain a timing signal S2 in the form of a rectangular wave with a steep rise as shown in FIG. 4C between the output terminal T0 and the ground.

However, since it has a resistor R2 connected in parallel to Josephson junction JS,
After JS is transferred to the voltage-carrying state by the current I2, the Josephson junction J _k of the series circuit U2,
J _k+1 ,...J _N When current I _k flows through resistor R _k , a sinusoidal current I4 (not shown) corresponding to the waveform of input signal S1 is passed through resistor R2. This can be passed through the series circuit U2 as a bias current. For this reason, the transition of Josephson junctions J ₁ ′ to J _N ′ of the series circuit U2 mentioned above to the voltage state is as follows.
This is more steep and reliably obtained than in the case of FIG.

Therefore, according to the superconducting timing signal forming circuit according to the present invention shown in FIG. 5, the timing signal S2, which rises more steeply than in the case of FIG. 3, can be generated more reliably than in the case of FIG. It has the great feature that it can be obtained from the input signal S1.

Next, an example of a superconducting timing signal forming circuit according to the third invention of the present application will be described with reference to FIG. 6. Parts corresponding to those in FIG. Although omitted, in the configuration described above in Fig. 3, a third
It has the same structure as the case of FIG. 3, except that the resistor R3 is connected in series.

The above is an example of the configuration of the superconducting timing signal forming circuit according to the third invention of the present application.
Since it has the same configuration as the case shown in the figure, a detailed explanation thereof will be omitted, but similarly to the case shown in Fig. 3, a rectangular wave-like timing signal S2 with a steep rise can be obtained from a sinusoidal wave-like input signal S1. It is something that can be done.

However, since it has a resistor R3 connected in series with Josephson junction JS,
When JS transitions to a voltage state, even when current I2 flows through resistor R1 in series circuit U1, a sinusoidal current I5 (not shown) corresponding to the waveform of input signal S1 is generated. It can be applied to the series circuit U1 via the resistor R1.

For this reason, Josephson junction J ₁ ~ J _N of series circuit U1
The transition to the voltage-applied state is more steep and more reliable than in the case of FIG.

Therefore, according to the superconducting timing signal forming circuit according to the present invention shown in FIG. 6, the timing signal S2, which rises more steeply than in the case of FIG. 3, can be input more reliably than in the case of FIG. It has the great feature that it can be obtained from the signal S1.

Next, an example of a superconducting timing signal forming circuit according to the fourth invention of the present application will be described with reference to FIG. 7. Parts corresponding to those in FIG. Although omitted, in the configuration described above in Fig. 3, the fifth
As in the case of the figure, resistor R2 is connected in parallel,
It has the same configuration as the case shown in FIG. 3, except that the resistor R3 is connected in series as in the case shown in FIG.

The above is an example of the configuration of the superconducting timing signal forming circuit according to the fourth invention of the present application. 3, a rectangular wave timing signal S2 having a steeper rise can be obtained from the sinusoidal input signal S1, although a detailed explanation thereof will be omitted.

However, in the case of the superconducting timing signal forming circuit according to the present invention shown in FIG.
JS has a resistor R2 connected in parallel as in the case of Fig. 5, and a resistor R3 connected in series as in the case of Fig. 6, so in the case of Figs. Having both the above characteristics,
It has great characteristics.

In the above description, only one example has been described for each of the first to fourth inventions of the present application, and for example, a configuration in which an inductor is connected in series to the resistor R _k may be used, and other aspects of the spirit of the present invention may be used. Various modifications may be made without departing from the .

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing a conventional superconducting timing signal forming circuit, FIG. 2 is a signal waveform diagram for explaining the same, and FIG. 3 is an example of a superconducting timing signal forming circuit according to the first invention of the present application. 4 is a signal waveform diagram for explaining the connection diagram, and FIG. 5, FIG. 6, and FIG. 7 are examples of superconducting timing signal forming circuits according to the second, third, and fourth inventions of the present application, respectively. FIG. In the figure, J ₁ to J _N and J ₁ ′ to J _N ′ are Josephson junctions,
U1 and U2 are series circuits, JS is Josephson junction for trigger signal generation, R1, R2, R3 and R ₁
~R _N is the resistance, T1 is the input terminal, T0 is the output terminal, RL
indicates the load, respectively.

Claims (1)

[Scope of Claims] 1. A first series circuit in which a plurality of N Josephson junctions J ₁ , J ₂ , . . . J _N having substantially equal critical currents are connected in series; N Josephson junctions J ₁ ′ with equal critical currents,
and a second series circuit in which J ₂ ′, ...J _N ′ are connected in series, and from one end side of the first and second series circuits,
A common input terminal is led out through the respective first resistors and Josephson junctions for generating a trigger signal, and the other ends of the first and second series circuits are connected to ground, and the first series circuit A resistor R ₁ is connected between a midpoint of connection between the circuit and the first resistor and a midpoint of connection between the second series circuit and the Josephson junction for generating a trigger signal, and Josephson junctions J _i and J _(i+1) of the circuit (where i=1, 2,...
(N-1)) and the connection midpoint of Josephson junctions J _i ′ and J′ _(i+1) of the second series circuit, a resistor R _(i+1) is connected. A superconducting timing signal forming circuit characterized in that an output terminal is led out from a connection midpoint between the second series circuit and the Josephson junction for generating a trigger signal. 2. A first series circuit consisting of a plurality of N Josephson junctions J ₁ , J ₂ , ... J _N connected in series, each having substantially equal critical currents; N Josephson junctions J′ ₁ ,
and a second series circuit in which J ₂ ′, ...J _N ′ are connected in series, and from one end side of the first and second series circuits,
A common input terminal is led out through the respective first resistors and Josephson junctions for generating a trigger signal, and the other ends of the first and second series circuits are connected to ground, and the first series circuit A resistor R ₁ is connected between a midpoint of connection between the circuit and the first resistor and a midpoint of connection between the second series circuit and the Josephson junction for generating a trigger signal, and Josephson junctions J _i and J _(i+1) of the circuit (where i=1, 2,...
(N-1)) and the connection midpoint of Josephson junctions J _i ′ and J′ _(i+1) of the second series circuit, a resistor R _(i+1) is connected. and an output terminal is led out from the midpoint of the connection between the second series circuit and the Josephson junction for generating the trigger signal, and a second resistor is connected in parallel to the Josephson junction for generating the trigger signal. Features a superconducting timing signal forming circuit. 3. A first series circuit in which a plurality of N Josephson junctions J ₁ , J ₂ ...J _N having substantially equal critical currents are connected in series, and a plurality N Josephson junctions having substantially equal critical currents each other. Josephson junctions J ₁ ′, J ₂ ′,
. . . and a second series circuit in which J _N ' are connected in series, and from one end side of the first and second series circuits,
A common input terminal is led out through the respective first resistors and Josephson junctions for generating a trigger signal, and the other ends of the first and second series circuits are connected to ground, and the first series circuit A resistor R ₁ is connected between a midpoint of connection between the circuit and the first resistor and a midpoint of connection between the second series circuit and the Josephson junction for generating a trigger signal, and Josephson junctions J _i and J _(i+1) of the circuit (where i=1, 2,...
(N-1)) and the connection midpoint of Josephson junctions J _i ′ and J′ _(i+1) of the second series circuit, a resistor R _(i+1) is connected. and an output terminal is led out from the midpoint of connection between the second series circuit and the Josephson junction for generating a trigger signal, and a third resistor is connected in series with the Josephson junction for generating the trigger signal. Features a superconducting timing signal forming circuit. 4. A first series circuit consisting of a plurality of N Josephson junctions J ₁ , J ₂ , ... J _N connected in series, each having substantially equal critical currents, and a plurality of N Josephson junctions having substantially equal critical currents N Josephson junctions J ₁ ′,
and a second series circuit in which J ₂ ′, ...J _N ′ are connected in series, and from one end side of the first and second series circuits,
A common input terminal is led out through the respective first resistors and Josephson junctions for generating a trigger signal, and the other ends of the first and second series circuits are connected to ground, and the first series circuit A resistor R ₁ is connected between a midpoint of connection between the circuit and the first resistor and a midpoint of connection between the second series circuit and the Josephson junction for generating a trigger signal, and Josephson junctions J _i and J _(i+1) of the circuit (where i=1, 2,...
(N-1)) and the connection midpoint of Josephson junctions J _i ′ and J′ _(i+1) of the second series circuit, a resistor R _(i+1) is connected. An output terminal is led out from the connection midpoint between the second series circuit and the Josephson junction for generating a trigger signal, a second resistor is connected in parallel to the Josephson junction for generating the trigger signal, and a third resistor is connected in parallel to the Josephson junction for generating the trigger signal. A superconducting timing signal forming circuit characterized by resistors connected in series.