JPS6353479B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a time delay electric detonator that extends the time from activation to ignition. In a time delay electric detonator, a time delay circuit (hereinafter referred to as "delay circuit") is constructed by connecting the ignition resistance wire and the power supply through a thyristor, and connecting the gate of the thyristor to a delay circuit consisting of a resistor and a capacitor through a switching diode. An electric detonator having an analog method) is described in Japanese Patent Publication No. 48-23887 and Japanese Patent Application Laid-open No.
It is known from the publication No. 54-43454. In an analog time delay circuit, the delay time is determined by a resistor, a capacitor, and a switch diode that make up the delay circuit. In order to obtain different extension times, it is necessary to change the constant of at least one of these components. Therefore, in order to manufacture many types of ignition devices with different elongation times, many types of parts with different constants must be prepared. For example, according to the embodiment described in JP-A No. 54-43454, the applied voltage is 5V, the operating voltage of the switch diode is 2V, and the capacitor capacity is 1μF.
The relationship between the elapsed time, that is, seconds, and the resistance value is as follows.

[Table] In other words, resistors with different values are used depending on the value of the elapsed time, and the types of resistors are the same as the number of seconds, and in the above example, 20 types are required. When manufacturing detonators, it is not desirable to handle such a large variety of parts. For example, inspections have to be conducted by type, which increases the number of inspections required, increases the need for equipment to prevent parts with different values from mixing with each other, or requires management work such as double checking. This unavoidable inconvenience, such as sagging, reduces the effectiveness of mass production in terms of both price and productivity. Furthermore, the accuracy of the time elapsed time in the detonator is required to ensure that the second time variation distributions of products in adjacent stages do not overlap. For example, the difference in seconds between the 10th and 11th stages is 10 milliseconds (msec), so the seconds on the 10th stage are less than 90 + 5msec, and the seconds on the 11th stage are 100 -
Must be 5msec or more. In other words, an accuracy of 4.5% is required for the 10th stage and 5% for the 11th stage.
On the other hand, industrially used resistors and capacitors generally have an accuracy within ±5%, and the same applies to the reverse voltage of a switch diode. Therefore, these parts used in analog time delay circuits must be selected to ensure uniform accuracy, which inevitably increases manufacturing costs.
For the same reason, it is difficult to economically mass-produce a time delay electric detonator with high precision, for example, a time delay error of ±1% or less, using an analog time delay circuit. Further, as shown in the above table, the constants of these electric parts have special values, and there are no commercially available products, so it is necessary to make them specially for this time delay circuit, which makes them expensive. Further, in an analog time delay circuit, the delay time is affected by the voltage value applied to the circuit. Therefore, it is necessary to use an expensive power source with stable voltage as the power source for the electric detonator, that is, the power source for the blaster. It is an object of the present invention to solve the above-mentioned problems of analog type electric detonators. That is, it is an object of the present invention to reduce the number of parts by reducing the number of parts that determine the time difference in seconds, to facilitate adjustment, to increase the effectiveness of mass production, and at the same time to avoid an increase in costs. According to this invention, a digital timer is used which starts its operation upon application of a voltage, and the output of this timer turns on a switching circuit, causing current to flow through the ignition resistance wire through the switching circuit. This digital timer includes a digital counter that counts the reference time signal, and the period of the reference time signal is determined as follows. In general, the second time difference between stage detonators is made up of an integral multiple of the second stage corresponding to the second stage as a reference time. For example, Japanese Industrial Standard JIS K4807
1978 (table below)

In the DS detonator time series shown in [Table], the minimum second time difference between adjacent stages is 0.25 seconds, the third stage has a time difference of 0.5 seconds,
Below, the 9th stage is 2.00 seconds, the 10th stage is 2.30 seconds, and each time the number of stages increases, it becomes longer by 0.25 seconds.
Although the second time difference of the 10th stage is not exactly an integral multiple of 0.25 seconds, there is no real difference when looking at the distribution of second time differences of actual products. Furthermore, in the time series of MS detonators, the minimum second time difference is 1 millisecond, as shown in the table above. This invention utilizes the fact that the elapsed time of each stage has such a relationship. That is, a reference time signal having a period equal to the minimum second time difference in one elapsed time series is generated by a reference time signal generation circuit, and this reference time signal is counted by a digital counter. This counter is, for example, a decimal counter, and sequentially generates intermediate outputs at corresponding intermediate output terminals after an integer multiple of the minimum second time difference has elapsed. The intermediate output terminal of the counter corresponding to the desired second time (extension time) is selected and connected to the switching circuit as a timer output terminal. In this way, by using a circuit that selects one of the intermediate output terminals of the counter as the stage number setting circuit and connects it to the digital timer output terminal,
All stages of seconds can be created using the same reference time signal generation circuit, the same counter, and the same stage number setting circuit. In order to manufacture the DS detonator and MS detonator specified in the JIS, the analog method requires 20 types of resistors, one type of capacitor, and a switch diode, but according to the electric detonator of this invention, the detonator 2 compatible with 250msec
10 kinds of reference signal generation circuit and one kind of intermediate output
All you need is a forward counter. That is, in the electric detonator of the present invention, the types of parts used can be significantly reduced, so that it is possible to avoid the deterioration in mass production and the increase in parts cost, which are the drawbacks of the analog system described above. In addition, by using an appropriate resonant element in the reference time signal generation circuit, the accuracy of the seconds can be increased at a relatively low cost, and it will operate correctly even if the power supply voltage fluctuates to some extent. An inexpensive power supply device can be used. Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 shows the basic structure of a time delay electric detonator according to the present invention. Tube 1 contains ignition powder 2 (only a portion is listed)
, an ignition resistance wire 3 , and a switching circuit 4 connected in series with the ignition resistance wire 3 are housed therein, and the tube body 1 is plugged with an embolus 8 . Leg wires 7a and 7b are introduced into the embolus 8 from the outside, and a series circuit of the ignition resistance wire 3 and the switching circuit 4 is connected between the leg wires 7a and 7b. In this invention, a digital timer 5 is housed within the tubular body 1, the output side of the timer 5 is connected to the control input side of the switching circuit 4, and the timer 5 and the switching circuit 4 constitute a delay circuit 6. The digital timer 5 has a reference time signal generation circuit 9 having an oscillator 11 and a digital counter 12 for counting the reference time signal, and the number of stages that can be selectively connected to the output side of the timer 5 is set. It is composed of a circuit 10. FIG. 2 shows a specific example of the time delay circuit 6 shown in FIG. In FIG. 2, the power supply and grounding in the circuit are omitted except for some parts. When an external power source is connected to the leg wires 7a and 7b, the thyristor 41 constituting the switch circuit 4 is in a cutoff state, no current is supplied to the ignition resistance wire 3, and no ignition is performed. At the same time as connecting the power supply, other parts of the delay circuit 6 are connected to the wire 13.
Once the power is connected through, it will start working. Subsequently, when the seconds determined by the reference time signal generation circuit 9 and the stage number setting circuit 10 have elapsed, that is, the elapsed time, an ignition signal is generated, and the thyristor 41 is made conductive and the ignition resistance wire 3 is connected to the ignition resistance wire 3. Turn on the electricity and ignite it. Next, the configuration and operation of each part will be sequentially explained. The reference time signal generation circuit 9 is composed of an oscillator 11, a multistage binary counter 16 that divides the frequency of its output, and the like. The oscillator 11 includes, for example, an inverter 14, a ceramic vibrator 15, a resistive element, and a capacitor, and generates a rectangular wave signal of, for example, 32768 Hz. This signal is input to the multi-stage binary counter 16, and the
The output of the reference time signal generation circuit 9 is taken out from the output terminal 17 of the 13th stage. This output is simultaneously supplied via an OR gate 18 to a reset input terminal 19 of the counter 16. As a result, one pulse is generated at the output terminal 17 every time the input rectangular wave signal is counted 2^13 times. That is, a pulse train having a period of (1/32786) seconds×(2) ¹³ =0.25 seconds is taken out from the output terminal 17 and used as a reference time signal. The stage number setting circuit 10 includes a multistage decimal counter 12 with a decoder, a switching circuit 20, and an output circuit 21. The decimal counter 12 has 10 intermediate output terminals 2.
2-1, 22-2, ...22-10 are provided, and these intermediate output terminals 22-1, ...22-
10, outputs are sequentially obtained from different terminals each time a reference time signal is input, as shown in FIG. That is, after the reset signal shown in FIG. 3A ends, by detecting the falling edge of the trailing edge of the pulse of the output signal of the intermediate output terminal, the number of pulses of the input signal of FIG. 3B, that is, the reference time signal, can be determined. For example, the output terminal 22-1 falls when the first pulse is input as shown in FIG. 3C, and the output terminal 22-3 falls when the third pulse is input as shown in FIG. 3E. Falling with input pulse, intermediate output terminals 22-1 to 22-
10, the outputs shown in FIGS. 3C to 3L are obtained. When inputting the reference time signal explained earlier,
A falling pulse is generated at the output terminal 22-1 and 0.75 seconds after the reset, respectively. These time intervals correspond to the seconds of the second and fourth stages of the DS electric detonator mentioned above, respectively. Therefore, the 10 output terminals 22 of the decimal counter 12
-1 to 22-10, select one corresponding to the desired number of stages and ignite the thyristor 41 of the switch circuit 4 with the output signal, then the ignition current will be applied to the ignition resistance wire 3 after the set time has elapsed. is supplied.
The switching circuit 20 thus selects the intermediate output terminals 22-1 to 22-10 of the counter 12 in accordance with the number of stages and connects them to the output side of the timer 5, and is determined and connected at the time of manufacturing the detonator. The output circuit 21 includes a resistor 21a and a capacitor 21
This is a well-known pulse generation circuit consisting of an integrating circuit 21c consisting of a C-MOS inverter 23, and a CMOS AND gate 24.The output of the switching circuit 20 is supplied to the integrating circuit 21c and the inverter 23, and these outputs are The signal is supplied to the gate 24, and a falling edge of the trailing edge of the output pulse of the counter 12 is detected to generate an ignition pulse at the output terminal 25 of the timer 5.
The ignition pulse is applied to the gate of the thyristor 41 through the current limiting resistor 4a, ignites the thyristor 41, and causes the ignition current to flow through the ignition resistance wire 3.
Resistor 4 between the gate and cathode of thyristor 41
b is for preventing malfunction of the thyristor 41. Binary counters 16 and 10 used in this example
The internal state of the advance counter 12 is generally undefined when the power is turned on, and in order to accurately operate the functions described above, it is necessary to initialize the counter 12 at the same time as the power is turned on. The reset circuit 26 is provided for this purpose, and utilizes the characteristics of the CMOS inverter 27 to generate a positive pulse at the output terminal 28 of the inverter 27 as soon as the power supply voltage is supplied to the legs 7a, 7b. This is supplied to the reset terminal of the counter 12, and is also supplied to the counter 19 through the OR gate 18.
is supplied to the reset terminal 19 of the circuit to align the initial state. At the same time, the output of terminal 28 is output from inverter 2.
9, a negative pulse is generated at its output terminal 30, which is applied to AND gate 24 to inhibit its output and prevent thyristor 41 from being erroneously fired upon power-up. Then resistor 26
a. After a time determined by the time constant of the capacitor 26b, the outputs of the inverters 27 and 29 are inverted and each part starts operating. The diode 26c is for preventing backflow. As is clear from the above description, according to this embodiment, one type of oscillator and one type of binary counter are used to generate the reference time signal, and the output thereof is sent to one type of decimal counter with a decoder. By counting at 12 and igniting the switch element 4 with a signal from the intermediate output terminal corresponding to the number of stages, a stage generator detonator having an arbitrary number of stages with a second time difference consisting of an integral multiple of the reference time is constructed. can. That is, unlike the analog system, there is no need to prepare many types of reference time components corresponding to various numbers of stages. In this case, it is sufficient to simply change one oscillator according to the extended time series. In this example, the error is ±0.3 for the reference time of 0.25 seconds.
%was gotten. This accuracy is determined by the accuracy of the ceramic resonator 15 used. FIG. 4 shows an embodiment using another configuration of the reference time signal generating circuit 9. In FIG. This example can be used when high precision is not required as in the previous example. The output of an astable multivibrator oscillator 11 consisting of two CMOS inverters 31 and 32, a resistor 11a, and a capacitor 11b is used as a reference time signal and input to the stage number setting circuit 10. Other operations, stage number settings, etc. are the same as in the previous example. The reference time is the resistance value R ₀ of the resistor 11a and the capacitance of the capacitor 11b.
For example, when R ₀ = 2.5 MΩ and C ₀ = 0.0047 μF, 25 milliseconds is obtained, and its accuracy is determined by the accuracy of R _{0 C 0 .} In order to connect a plurality of such electric detonators in series and fire multiple shots at once, each electric detonator must have a fifth
As shown in the figure, an energy storage capacitor 51 is connected between the leg lines 7a and 7b, and when multiple detonators are to be fired simultaneously, the capacitor 51 of each electric detonator is charged with a blaster, and the accumulated power of the capacitor 51 is used to generate a digital timer. 5 is driven, and its output turns on the switching circuit 4, causing current to flow from the capacitor 51 to the ignition resistance wire 3. Capacity C ₀ (μF) of this energy storage capacitor 51 and voltage E across it
In relation to (V), the limit that can be ignited is shown by the curve E=160×C ₀ ^-0.684 shown in FIG. 6, and all detonators ignite above this line.
Therefore, the capacitance C ₀ must be adjusted to satisfy E≧160×C ₀ ^-0.684 .
It is preferable to select Especially capacitor 51
In order to use an electrolytic capacitor as an electric field capacitor and not to make it too large, it is desirable to use a capacitor of 100 μF or less, and to not increase the power supply voltage of the blaster too much, it is desirable to use a capacitor of 10 μF.
The above is preferable. In the figure, ○ indicates firing, and × indicates non-ignition. An example of the structure of this electric detonator is shown in FIG. A charge 53 is placed inside the tube body 1, and a detonator 54 is also placed inside the tube body 1.
The inner tube 55 loaded with the same is inserted and plugged with an embolus 8. The embolus 8 has a built-in capacitor 51, which is a molded product made of, for example, a synthetic resin material, to which the leg wires 7a and 7b are connected. A molded part 57 of the timer 5 and the switching circuit 4 is also embedded in the embolus 8. An ignition resistance wire 3 is attached to the inner end of the embolus 8, an ignition ball 58 is attached to the resistance wire 3, and a coating 59 is applied thereon. As is clear from the above description, according to the present invention, it is possible to manufacture a time delay electric detonator with an arbitrary second time difference (number of steps) based on one reference time. In other words, the number of components that determine the second time difference, such as resistors and capacitors, can be significantly reduced. This improves the mass productivity of the extended-time electric detonator and prevents increases in manufacturing costs. or,
It is possible to improve the accuracy of seconds at a relatively low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the time delay electric detonator according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the digital timer 5, and FIG. A time chart showing the relationship with the output, Figure 4 is a circuit diagram showing a specific example of timer 5 using a reference time signal generation circuit using a resistor and a capacitor, and Figure 5 is an electrical diagram showing the connection of an energy storage capacitor. 6 is a voltage-capacity characteristic curve diagram showing the ignition limit of the electric detonator shown in FIG. 5; FIG. 7 is a sectional view showing an example of the structure of the electric detonator of the present invention. . 1: Pipe body, 2: Ignition powder, 3: Resistance wire for ignition,
4: Switching line, 5: Digital timer,
6: delay circuit, 7a, 7b: leg line, 8: embolus,
9: Reference time signal generation circuit, 10: Stage number setting circuit, 11: Oscillator, 12: Counter, 15: Oscillator, 26: Reset circuit.

Claims (1)

[Scope of Claims] 1. An ignition resistance wire, a digital timer that generates an output signal when a desired delay time has elapsed after startup, and the ignition resistance wire which becomes closed when the output signal of the digital timer is applied. and a switching circuit for energizing. 2. The digital timer has a reference time signal generation circuit that generates a reference time signal whose cycle is the minimum second time difference in one elongated time series, and a plurality of intermediate output terminals that output a plurality of intermediate count values, It is characterized by comprising a multistage counter that counts signals, and a stage number setting circuit that selects and uses one of the intermediate output terminals to generate an output signal after a delay time that is an integral multiple of the reference time has elapsed. A time-duration electric detonator according to claim 1.