JPS6355109U - - Google Patents
Info
- Publication number
- JPS6355109U JPS6355109U JP14969086U JP14969086U JPS6355109U JP S6355109 U JPS6355109 U JP S6355109U JP 14969086 U JP14969086 U JP 14969086U JP 14969086 U JP14969086 U JP 14969086U JP S6355109 U JPS6355109 U JP S6355109U
- Authority
- JP
- Japan
- Prior art keywords
- detection coil
- output
- flip
- applying
- magnetostrictive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 8
Landscapes
- Length Measuring Devices Characterised By Use Of Acoustic Means (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Description
第１図は本考案に係る磁歪信号検出回路の一実
施例の接続図、第２図は第１図のタイミングチヤ
ート、第３図は第１図の動作を説明する為の波形
図、第４図は磁歪信号検出回路の動作原理を説明
する為の図、第５図は第４図の動作を説明する為
の図、第６図は従来装置の動作を説明する為の波
形図、第７図は本考案を説明する為の磁歪信号検
出回路の回路図、第８図は第７図回路のタイミン
グチヤート、第９図は第７図回路の動作を説明す
る為の波形図である。
１…磁歪線、２…駆動コイル、３…検出コイル
、４…直接波、５…反射波、ＣＯＭＰ，ＣＯＭＰ
２…比較器、ＦＦ１，ＦＦ２…フリツプ・フロツ
プ、ＤＬ…遅れ回路。
FIG. 1 is a connection diagram of an embodiment of the magnetostrictive signal detection circuit according to the present invention, FIG. 2 is a timing chart of FIG. 1, FIG. 3 is a waveform diagram for explaining the operation of FIG. 1, and FIG. The figure is a diagram for explaining the operating principle of the magnetostrictive signal detection circuit, Figure 5 is a diagram for explaining the operation of Figure 4, Figure 6 is a waveform diagram for explaining the operation of the conventional device, and Figure 7 is a diagram for explaining the operation of the conventional device. The figure is a circuit diagram of a magnetostrictive signal detection circuit for explaining the present invention, FIG. 8 is a timing chart of the circuit of FIG. 7, and FIG. 9 is a waveform diagram for explaining the operation of the circuit of FIG. 7. 1...Magnetostrictive wire, 2...Drive coil, 3...Detection coil, 4...Direct wave, 5...Reflected wave, COMP, COMP
2...Comparator, FF1, FF2...Flip-flop, DL...Delay circuit.
Claims (1)
配置された磁歪線を有し、前記磁歪線の一端に駆
動パルスを与えることにより発生する縦弾性波が
磁歪線を伝播し前記検出コイルに直接到達するま
での時間ｔ１と磁歪線の開放端部で反射して検出
コイルに到達するまでの時間ｔ２を前記検出コイ
ルを用いて検出するようにした磁歪信号検出回路
において、 直接波が検出コイルに加わることによりこの検
出コイルにおいて最初に発生するプラスのパルス
出力ａｄと、反射波が検出コイルに加わることに
よりこの検出コイルにおいて発生する２番目のプ
ラスのパルスｂｒとを一定のスレツシヨールド・
レベルと比較する比較器、駆動パルスによりセツ
トされクロツク入力として前記比較器の出力が与
えられる第１、第２のフリツプ・フロツプ、第１
のフリツプ・フロツプの出力端子に接続された遅
れ回路、及びこの遅れ回路の出力を一定のスレツ
シヨールド・レベルと比較しその出力が第２のフ
リツプ・フロツプのデータ入力端子に加えられる
第２の比較器よりなり、前記第１、第２のフリツ
プ・フロツプの出力端より時間ｔ１，ｔ２に対応
した信号を得るようにしたことを特徴とする磁歪
信号検出回路。[Claims for Utility Model Registration] It has a magnetostrictive wire in which a detection coil is arranged so as to be movable in the length direction, and the longitudinal elastic wave generated by applying a driving pulse to one end of the magnetostrictive wire is A magnetostrictive signal detection circuit configured to use the detection coil to detect a time t1 for the magnetostrictive wire to propagate and directly reach the detection coil, and a time t2 for the magnetostrictive wire to reflect at an open end and reach the detection coil. , the first positive pulse output a d is generated in this detection coil by applying a direct wave to the detection coil, and the second positive pulse b r is generated in this detection coil by applying a reflected wave to the detection coil. and a certain threshold
a comparator for comparison with the level; a first and a second flip-flop set by a drive pulse and having the output of said comparator as a clock input;
a delay circuit connected to the output terminal of the second flip-flop; and a second comparator for comparing the output of the delay circuit with a fixed threshold level and applying the output to the data input terminal of the second flip-flop. A magnetostrictive signal detection circuit characterized in that signals corresponding to times t1 and t2 are obtained from the output terminals of the first and second flip-flops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14969086U JPH04265Y2 (en) | 1986-09-30 | 1986-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14969086U JPH04265Y2 (en) | 1986-09-30 | 1986-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6355109U true JPS6355109U (en) | 1988-04-13 |
| JPH04265Y2 JPH04265Y2 (en) | 1992-01-07 |
Family
ID=31065138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14969086U Expired JPH04265Y2 (en) | 1986-09-30 | 1986-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04265Y2 (en) |
-
1986
- 1986-09-30 JP JP14969086U patent/JPH04265Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04265Y2 (en) | 1992-01-07 |
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