JPS6356455U - - Google Patents
Info
- Publication number
- JPS6356455U JPS6356455U JP15057186U JP15057186U JPS6356455U JP S6356455 U JPS6356455 U JP S6356455U JP 15057186 U JP15057186 U JP 15057186U JP 15057186 U JP15057186 U JP 15057186U JP S6356455 U JPS6356455 U JP S6356455U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- dma
- outputting
- control
- system circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Bus Control (AREA)
Description
第１〜３図は本考案のＤＡＭ系回路検査装置の
一実施例を示す図であり、第１図はそのＤＡＭ系
回路検査装置の回路図、第２図はそのＤＡＭ系回
路検査装置を被検査回路に取り付けた状態のブロ
ツク図、第３図はそのＤＡＭ系回路検査装置の入
出力信号の波形図である。
１……ＤＭＡ系回路検査装置、２……ＣＰＵ、
３……ＤＭＡ制御素子、１３……ＤＭＡ終了信号
出力回路（ＤＭＡ終了信号出力手段）、１４ａ〜
１４ｈ……チエツクピン（出力手段）、１５……
起動手段。
1 to 3 are diagrams showing an embodiment of the DAM circuit testing device of the present invention, FIG. 1 is a circuit diagram of the DAM circuit testing device, and FIG. 2 is a circuit diagram of the DAM circuit testing device. FIG. 3 is a block diagram of the device installed in a test circuit, and is a waveform diagram of input and output signals of the DAM circuit test device. 1...DMA system circuit inspection device, 2...CPU,
3...DMA control element, 13...DMA end signal output circuit (DMA end signal output means), 14a~
14h...Check pin (output means), 15...
Starting means.
Claims (1)
Ａ要求信号を出力する起動手段と、ＤＭＡ制御素
子からの一定の制御信号に基づいてＤＭＡ終了を
表示する信号を出力するＤＭＡ終了信号出力手段
と、上記制御信号を外部に取り出すための出力手
段と、を備えたことを特徴とするＤＭＡ系回路検
査装置。 (2) 前記ＤＭＡ終了信号出力手段に制御信号と
して、ＤＭＡ肯定応答信号、Ｉ／Ｏリード信号、
Ｉ／Ｏライト信号、メモリリード信号、メモリラ
イト信号が入力されることを特徴とする実用新案
登録請求の範囲第１項記載のＤＭＡ系回路検査装
置。[Claims for Utility Model Registration] (1) Continuous DM control at predetermined intervals in the DMA control element
A activating means for outputting an A request signal, a DMA end signal outputting means for outputting a signal indicating the end of DMA based on a certain control signal from a DMA control element, and an outputting means for taking out the control signal to the outside. A DMA system circuit inspection device comprising: (2) A DMA acknowledgment signal, an I/O read signal, a DMA acknowledgment signal, an I/O read signal,
The DMA system circuit testing device according to claim 1, wherein an I/O write signal, a memory read signal, and a memory write signal are input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15057186U JPS6356455U (en) | 1986-09-30 | 1986-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15057186U JPS6356455U (en) | 1986-09-30 | 1986-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6356455U true JPS6356455U (en) | 1988-04-15 |
Family
ID=31066833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15057186U Pending JPS6356455U (en) | 1986-09-30 | 1986-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356455U (en) |
-
1986
- 1986-09-30 JP JP15057186U patent/JPS6356455U/ja active Pending
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