JPS6356834U - - Google Patents

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Publication number
JPS6356834U
JPS6356834U JP15187686U JP15187686U JPS6356834U JP S6356834 U JPS6356834 U JP S6356834U JP 15187686 U JP15187686 U JP 15187686U JP 15187686 U JP15187686 U JP 15187686U JP S6356834 U JPS6356834 U JP S6356834U
Authority
JP
Japan
Prior art keywords
converter
selection line
signal selection
data
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15187686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15187686U priority Critical patent/JPS6356834U/ja
Publication of JPS6356834U publication Critical patent/JPS6356834U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す構成図、第2
図はマイクロコンピユータ側のフローチヤート、
第3図は従来のA/D変換器の構成図、第4図は
マイクロコンピユータ側のフローチヤートである
。 図中、C0〜C2は信号選択線、EXCは入出
力切換部、LATはアドレスラツチ、CH0〜C
H7はアナログ信号、CMPは電圧比較器、MP
Xはマルチプレクサ、SARは逐次比較レジスタ
、SRはシフトレジスタ、DATA OUTはシ
リアルデータ、DDRは入出力指定信号である。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a flowchart on the microcomputer side.
FIG. 3 is a block diagram of a conventional A/D converter, and FIG. 4 is a flowchart on the microcomputer side. In the figure, C0 to C2 are signal selection lines, EXC is an input/output switching section, LAT is an address latch, and CH0 to C
H7 is an analog signal, CMP is a voltage comparator, MP
X is a multiplexer, SAR is a successive approximation register, SR is a shift register, DATA OUT is serial data, and DDR is an input/output designation signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数チヤネルのアナログ信号の1つが外部から
の信号選択線で指定され、そのA/D変換データ
をシリアルに出力するA/D変換器において、該
データの一部を該信号選択線を通して出力する入
出力切換部を設けてなることを特徴とするA/D
変換器。
In an A/D converter that serially outputs A/D converted data when one of multiple channels of analog signals is designated by an external signal selection line, an input signal that outputs part of the data through the signal selection line is used. An A/D characterized by being provided with an output switching section
converter.
JP15187686U 1986-10-02 1986-10-02 Pending JPS6356834U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15187686U JPS6356834U (en) 1986-10-02 1986-10-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15187686U JPS6356834U (en) 1986-10-02 1986-10-02

Publications (1)

Publication Number Publication Date
JPS6356834U true JPS6356834U (en) 1988-04-15

Family

ID=31069341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15187686U Pending JPS6356834U (en) 1986-10-02 1986-10-02

Country Status (1)

Country Link
JP (1) JPS6356834U (en)

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