JPS6356873U - - Google Patents

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Publication number
JPS6356873U
JPS6356873U JP14863886U JP14863886U JPS6356873U JP S6356873 U JPS6356873 U JP S6356873U JP 14863886 U JP14863886 U JP 14863886U JP 14863886 U JP14863886 U JP 14863886U JP S6356873 U JPS6356873 U JP S6356873U
Authority
JP
Japan
Prior art keywords
terminal
input
flop
flip
scanning method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14863886U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14863886U priority Critical patent/JPS6356873U/ja
Publication of JPS6356873U publication Critical patent/JPS6356873U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係る走査方式判別
回路の構成図、第2図は上記回路の各所における
入出力信号波形を示す信号波形図、第3図は本考
案の他の実施例を示す回路構成図、第4図は従来
回路の構成図、第5図は従来回路における入出力
信号波形図である。 12……水平同期信号、13……垂直同期信号
、16……Dフリツプフロツプ。
FIG. 1 is a configuration diagram of a scanning method discrimination circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram showing input and output signal waveforms at various parts of the above circuit, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a circuit configuration diagram showing the conventional circuit, and FIG. 5 is an input/output signal waveform diagram in the conventional circuit. 12...Horizontal synchronization signal, 13...Vertical synchronization signal, 16...D flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] D端子に水平同期信号及びクロツク端子に垂直
同期信号、クリア端子ならびにプリセツト端子に
高レベル状態の信号が各々入力されるDフリツプ
フロツプを有し、これにより前記水平同期信号と
垂直同期信号の位相比較を行なうことにより、前
記DフリツプフロツプのQ端子出力を走査方式の
検出信号とすることを特徴とする走査方式判別回
路。
It has a D flip-flop to which a horizontal synchronizing signal is input to a D terminal, a vertical synchronizing signal is input to a clock terminal, and a high level signal is input to a clear terminal and a preset terminal. A scanning method discriminating circuit characterized in that by doing so, the Q terminal output of the D flip-flop is used as a scanning method detection signal.
JP14863886U 1986-09-30 1986-09-30 Pending JPS6356873U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14863886U JPS6356873U (en) 1986-09-30 1986-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14863886U JPS6356873U (en) 1986-09-30 1986-09-30

Publications (1)

Publication Number Publication Date
JPS6356873U true JPS6356873U (en) 1988-04-15

Family

ID=31063101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14863886U Pending JPS6356873U (en) 1986-09-30 1986-09-30

Country Status (1)

Country Link
JP (1) JPS6356873U (en)

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