JPS635730U - - Google Patents
Info
- Publication number
- JPS635730U JPS635730U JP9772586U JP9772586U JPS635730U JP S635730 U JPS635730 U JP S635730U JP 9772586 U JP9772586 U JP 9772586U JP 9772586 U JP9772586 U JP 9772586U JP S635730 U JPS635730 U JP S635730U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- voltage
- controlled oscillators
- power supply
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
Description
第１図は本考案の実施例の構成を示すブロツク
図、第２図は従来のＰＬＬの構成を示すブロツク
図である。
１：基準信号発振器、２：位相比較器、３：ル
ープフイルタ、４：第１ＶＣＯ、５：第２ＶＣＯ
、６：分周器、７：電源切換スイツチ、８：電源
端子、９，１０：遅延回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional PLL. 1: Reference signal oscillator, 2: Phase comparator, 3: Loop filter, 4: 1st VCO, 5: 2nd VCO
, 6: Frequency divider, 7: Power supply selector switch, 8: Power supply terminal, 9, 10: Delay circuit.
Claims (1)
と分周器と複数の電圧制御発振器とこの電圧制御
発振器の電源を切換えるスイツチとで構成される
位相同期回路において、前記複数の電圧制御発振
器の電源切換スイツチの出力側にそれぞれ遅延回
路を設けたことを特徴とする位相同期回路。 In a phase-locked circuit comprising a reference signal oscillator, a phase comparator, a loop filter, a frequency divider, a plurality of voltage-controlled oscillators, and a switch for switching the power supply of the voltage-controlled oscillators, a power supply changeover switch for the plurality of voltage-controlled oscillators is provided. A phase-locked circuit characterized in that a delay circuit is provided on each output side of the phase synchronization circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986097725U JPH0434589Y2 (en) | 1986-06-27 | 1986-06-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986097725U JPH0434589Y2 (en) | 1986-06-27 | 1986-06-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS635730U true JPS635730U (en) | 1988-01-14 |
| JPH0434589Y2 JPH0434589Y2 (en) | 1992-08-18 |
Family
ID=30964974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986097725U Expired JPH0434589Y2 (en) | 1986-06-27 | 1986-06-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434589Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018110421A (en) * | 2012-05-10 | 2018-07-12 | サムスン エレクトロニクス カンパニー リミテッド | Transceiver applying switching of phase locked loop and phase noise improvement technique |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56117437A (en) * | 1980-02-20 | 1981-09-14 | Toshiba Corp | Pll circuit |
-
1986
- 1986-06-27 JP JP1986097725U patent/JPH0434589Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56117437A (en) * | 1980-02-20 | 1981-09-14 | Toshiba Corp | Pll circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018110421A (en) * | 2012-05-10 | 2018-07-12 | サムスン エレクトロニクス カンパニー リミテッド | Transceiver applying switching of phase locked loop and phase noise improvement technique |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0434589Y2 (en) | 1992-08-18 |