JPS635767U - - Google Patents

Info

Publication number
JPS635767U
JPS635767U JP9886986U JP9886986U JPS635767U JP S635767 U JPS635767 U JP S635767U JP 9886986 U JP9886986 U JP 9886986U JP 9886986 U JP9886986 U JP 9886986U JP S635767 U JPS635767 U JP S635767U
Authority
JP
Japan
Prior art keywords
data
ram
image data
bright
dark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9886986U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9886986U priority Critical patent/JPS635767U/ja
Publication of JPS635767U publication Critical patent/JPS635767U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Image Signal Circuits (AREA)
  • Character Input (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの考案の一実施例を示し、第1図は画
像入力部の概略図、第2図はこの装置のブロツク
図、第3図は同作用を示すフローチヤートである
。 1は画像読取り手段、7はラツチ回路、8はD
MA制御回路、9は明RAM、10は暗RAM、
11はデータRAM、12は中央処理装置(CP
U)、13は出力ポート。
The drawings show one embodiment of this invention, with FIG. 1 being a schematic diagram of an image input section, FIG. 2 being a block diagram of this device, and FIG. 3 being a flowchart showing the same operation. 1 is an image reading means, 7 is a latch circuit, 8 is D
MA control circuit, 9 is bright RAM, 10 is dark RAM,
11 is a data RAM, 12 is a central processing unit (CP
U), 13 is an output port.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 画像読取り手段1が読取つた画像データをラツ
チ回路7でラツチした後、DMA制御回路8を用
いてデータRAM11へ転送すると共に、予め明
RAM9に記憶された明データ及び暗RAM10
に記憶された暗データをもとに中央処理装置(C
PU)12が補正値を演算し、かつ上記データR
AM11に記憶された画像データに補正を加えて
出力ポート13へ出力するようにしてなる画像入
力装置の補正回路。
After the image data read by the image reading means 1 is latched by the latch circuit 7, it is transferred to the data RAM 11 using the DMA control circuit 8, and the bright data previously stored in the bright RAM 9 and the dark RAM 10 are transferred.
Based on the dark data stored in the central processing unit (C
PU) 12 calculates the correction value and uses the above data R.
A correction circuit for an image input device that corrects image data stored in an AM 11 and outputs the corrected image data to an output port 13.
JP9886986U 1986-06-30 1986-06-30 Pending JPS635767U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9886986U JPS635767U (en) 1986-06-30 1986-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9886986U JPS635767U (en) 1986-06-30 1986-06-30

Publications (1)

Publication Number Publication Date
JPS635767U true JPS635767U (en) 1988-01-14

Family

ID=30967225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9886986U Pending JPS635767U (en) 1986-06-30 1986-06-30

Country Status (1)

Country Link
JP (1) JPS635767U (en)

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