JPS6360347B2 - - Google Patents

Info

Publication number
JPS6360347B2
JPS6360347B2 JP54126986A JP12698679A JPS6360347B2 JP S6360347 B2 JPS6360347 B2 JP S6360347B2 JP 54126986 A JP54126986 A JP 54126986A JP 12698679 A JP12698679 A JP 12698679A JP S6360347 B2 JPS6360347 B2 JP S6360347B2
Authority
JP
Japan
Prior art keywords
signal
circuit
output
signals
analog correlation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54126986A
Other languages
Japanese (ja)
Other versions
JPS5651682A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12698679A priority Critical patent/JPS5651682A/en
Publication of JPS5651682A publication Critical patent/JPS5651682A/en
Publication of JPS6360347B2 publication Critical patent/JPS6360347B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28Details of pulse systems
    • G01S7/285Receivers
    • G01S7/292Extracting wanted echo-signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Manipulation Of Pulses (AREA)
  • Radar Systems Or Details Thereof (AREA)

Description

【発明の詳細な説明】 例えば、レーダ装置における受信信号中には物
標信号の他に干渉波、雨及び海面反射等の不要な
信号が含まれている。この内、非周期的な干渉波
は連続相関を取ることにより解決出来、一方周期
的(表示器上において)な雨及び海面反射等の信
号は微分(所謂FTC)を施すことにより除去さ
れていた。然し乍ら、上記雨及び海面反射信号に
おいてもその立上りの速い信号やパルス幅の長い
信号は除去困難であり、又微分を施すことにより
物標信号が表示器上においてその立上り部だけで
表わされ、正確な情報が得られなかつた。
DETAILED DESCRIPTION OF THE INVENTION For example, a received signal in a radar device includes, in addition to a target signal, unnecessary signals such as interference waves, rain, and reflections from the sea surface. Among these, non-periodic interference waves can be solved by taking continuous correlation, while periodic (on the display) signals such as rain and sea surface reflections can be removed by applying differentiation (so-called FTC). . However, even in the above-mentioned rain and sea surface reflection signals, it is difficult to remove signals with fast rises or signals with long pulse widths, and by performing differentiation, the target signal is represented on the display only by the rise part. I couldn't get accurate information.

本発明は、上述の欠点を解消する装置を提供す
るもので、以下図面の実施例に基づいて詳細に説
明する。
The present invention provides a device which eliminates the above-mentioned drawbacks and will be explained in detail below on the basis of an embodiment of the drawing.

第1図は本発明による回路図で、1は探知電波
パルスを一定の繰返し周期で送波するアンテナ
で、2は送波時と受波時の信号路を切換える送受
信切換回路である。3は受信信号から直流成分を
除去して交流成分のみ取り出す直流成分除去回路
を示す。4及び5は信号を△tだけ遅らせる遅延
回路で、遅延回路4の出力端は遅延回路5の入力
端に接続されている。6及び7は、例えばダイオ
ード2個と抵抗から成るANDゲートのようなア
ナログ相関回路で、各々入力端イ,ロ及びハ,ニ
を有する。8は上記アナログ相関回路6及び7の
出力をORゲートする加算回路を示す。
FIG. 1 is a circuit diagram according to the present invention, in which numeral 1 is an antenna that transmits detection radio wave pulses at a constant repetition period, and numeral 2 is a transmission/reception switching circuit that switches the signal path during wave transmission and wave reception. 3 shows a DC component removal circuit that removes DC components from the received signal and extracts only AC components. 4 and 5 are delay circuits that delay the signal by Δt, and the output terminal of the delay circuit 4 is connected to the input terminal of the delay circuit 5. Reference numerals 6 and 7 are analog correlation circuits such as, for example, AND gates composed of two diodes and a resistor, each having input terminals A, B, C, and D. Reference numeral 8 denotes an adder circuit that performs an OR gate on the outputs of the analog correlation circuits 6 and 7.

第2図は各回路の波形図を示すもので、図中
b′はbを一部拡大したものである。
Figure 2 shows the waveform diagram of each circuit.
b' is a partially enlarged version of b.

上記の回路構成において、次にその動作につき
説明すれば、アンテナより受信された種々の情報
を含んだ信号a(第2図)は送受切換回路2を経
て直流成分除去回路において信号bの如く交流成
分のみが抽出される。信号R1,R2は実例に基づ
く代表的な雨及び海面反射による信号、S1は物標
からの反射信号を示す。一般に、不要反射波は、
波形R1,R2に示すように、三角状波が出現し、
物標反射波は、波形S1に示すように、矩形状の波
形が出現する。
In the above circuit configuration, the operation thereof will be explained next. Signal a (Fig. 2) containing various information received from the antenna passes through the transmission/reception switching circuit 2, and then is converted to AC signal b in the DC component removal circuit. Only the components are extracted. Signals R 1 and R 2 are representative signals from actual rain and sea surface reflection, and S 1 is a reflection signal from a target object. Generally, unnecessary reflected waves are
As shown in waveforms R 1 and R 2 , triangular waves appear,
The target reflected wave appears as a rectangular waveform, as shown in waveform S1 .

さて、直流成分除去回路3の送出信号b′(すな
わち信号b)中に含まれる信号R1,S1及びR2
アナログ相関回路6の入力端イに送入されると共
に遅延回路4に送り込まれ、△t時間だけ遅延せ
しめられる。この出力信号Cはアナログ相関回路
6の入力端ロに送入され、出力として信号eを得
る。アナログ相関回路6は、波形図eから明らか
なように、直流成分除去出力b′と遅延出力cを比
較して両信号のうちレベルの低い方を選出する。
一方、上記信号Cはアナログ相関回路7の入力端
ハに送入されると共に遅延回路5に送り込まれ、
さらに△t時間だけ遅延せしめられて、出力側に
信号dを送出する。上記信号dはアナログ相関回
路7の入力端ニに送入され、出力として信号fを
得る。アナログ相関回路7は、波形図fから明ら
かなように、遅延出力cとbを比較して両信号の
レベルの低い方を選出する。その結果、アナログ
相関回路6並びに7の各出力e,fは遅延回路
4,5に設定された遅延時間Δtに基づいてパル
ス高及び巾の制限を施される。さらに、上記の信
号e及びfはORゲートの加算回路8に送入され
る結果信号gを得る。加算回路8は、波形gから
明らかなように、両信号e,fのうちレベルの高
い方の信号を選出する。これは第2図e,f,g
からも明らかな如く、雨及び海面反射信号R1
R2は各々パルス高に制限を受けて信号R′1,R′2
如く変換せしめられる。
Now, the signals R 1 , S 1 and R 2 included in the output signal b' (that is, signal b) of the DC component removal circuit 3 are sent to the input terminal A of the analog correlation circuit 6 and are also sent to the delay circuit 4. and is delayed by Δt time. This output signal C is sent to the input terminal RO of the analog correlation circuit 6, and a signal e is obtained as an output. As is clear from the waveform diagram e, the analog correlation circuit 6 compares the DC component removed output b' and the delayed output c and selects the one with the lower level of both signals.
On the other hand, the signal C is sent to the input terminal C of the analog correlation circuit 7, and is also sent to the delay circuit 5.
The signal d is further delayed by Δt time and sent to the output side. The signal d is sent to the input terminal 2 of the analog correlation circuit 7, and the signal f is obtained as an output. As is clear from the waveform diagram f, the analog correlation circuit 7 compares the delayed outputs c and b and selects the one with the lower level of both signals. As a result, the outputs e and f of the analog correlation circuits 6 and 7 are limited in pulse height and width based on the delay time Δt set in the delay circuits 4 and 5. Furthermore, the above signals e and f obtain a result signal g which is fed to the adder circuit 8 of the OR gate. As is clear from the waveform g, the adder circuit 8 selects the higher level signal from the two signals e and f. This is Figure 2 e, f, g
As is clear from the above, the rain and sea surface reflection signals R 1 ,
R 2 is converted into signals R' 1 and R' 2 with each pulse height being limited.

一方、物標信号S1は加算回路8の出力信号S′1
の如く△t時間だけ遅延される。
On the other hand, the target signal S 1 is the output signal S′ 1 of the adder circuit 8
It is delayed by Δt time as shown in FIG.

このように、本発明によれば、パルス幅を変化
させることなく、雨及び海面反射等の不要信号の
みそのレベルを押えることが出来、従つて、輝度
変調の結果ブラウン管上で物標信号との識別が極
めて容易になる。
As described above, according to the present invention, it is possible to suppress the level of unnecessary signals such as rain and sea surface reflection without changing the pulse width, and therefore, as a result of brightness modulation, it is possible to suppress the level of unnecessary signals such as rain and sea surface reflection. Identification becomes extremely easy.

又、ブラウン管上での最適の識別状態を設定す
るために遅延量△tを可変しても物標信号のパル
ス幅、パルス高が変化することはない。すなわ
ち、物標信号に関しては波形変形を行なうことな
く常に受信信号のままブラウン管上に表示出来
る。
Further, even if the delay amount Δt is varied in order to set the optimum discrimination state on the cathode ray tube, the pulse width and pulse height of the target signal do not change. That is, the target signal can always be displayed on the cathode ray tube as the received signal without waveform modification.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図で、第
2図は各回路の波形図である。 3は直流除去回路、4及び5は遅延回路、6及
び7はアナログ相関回路、8は加算回路、R1
びR2は雨及び海面反射信号、S1は物標信号。
FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram of each circuit. 3 is a DC removal circuit, 4 and 5 are delay circuits, 6 and 7 are analog correlation circuits, 8 is an addition circuit, R 1 and R 2 are rain and sea surface reflection signals, and S 1 is a target signal.

Claims (1)

【特許請求の範囲】 1 探知パルスを繰返し送信して探知物標からの
反射波を受信する送受信装置と、 該送受信装置から出力される受信信号中から直
流成分を除去して交流成分のみ抽出する交流成分
抽出回路と、 該交流成分抽出回路の出力信号を遅延させる第
1の遅延回路と、該第1の遅延回路の遅延出力を
さらに遅延させる第2の遅延回路と、該第1遅延
回路の遅延出力と上記交流成分抽出出力とを比較
して両信号のうちレベルの低い方の信号を選出す
る第1のアナログ相関回路と、上記第1遅延出力
と第2遅延出力とを比較して両信号のうちレベル
の低い方の信号を選出する第2のアナログ相関回
路と、該第1及び第2のアナログ相関回路の各選
出出力を比較して両出力信号のうちレベルの高い
方の信号を選出する加算回路とで構成され、物標
信号に比して信号の立上り、立下り部が比較的緩
慢な不要信号の振幅を抑圧する振幅抑圧回路と、 該振幅抑圧回路の出力信号を表示する表示器と
を具備してなるレーダー装置。
[Scope of Claims] 1. A transmitting/receiving device that repeatedly transmits detection pulses and receives reflected waves from detected targets, and which removes the DC component from the received signal output from the transmitting/receiving device and extracts only the AC component. an AC component extraction circuit; a first delay circuit that delays the output signal of the AC component extraction circuit; a second delay circuit that further delays the delayed output of the first delay circuit; a first analog correlation circuit that compares the delayed output and the AC component extraction output and selects a signal with a lower level among both signals; A second analog correlation circuit selects a signal with a lower level among the signals, and compares each selected output of the first and second analog correlation circuits to select a signal with a higher level among both output signals. an amplitude suppression circuit that suppresses the amplitude of an unnecessary signal whose rising and falling parts are relatively slow compared to the target signal; and an output signal of the amplitude suppression circuit. A radar device comprising a display device.
JP12698679A 1979-10-01 1979-10-01 Unnecessary-reflected-wave eliminator of radar device Granted JPS5651682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12698679A JPS5651682A (en) 1979-10-01 1979-10-01 Unnecessary-reflected-wave eliminator of radar device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12698679A JPS5651682A (en) 1979-10-01 1979-10-01 Unnecessary-reflected-wave eliminator of radar device

Publications (2)

Publication Number Publication Date
JPS5651682A JPS5651682A (en) 1981-05-09
JPS6360347B2 true JPS6360347B2 (en) 1988-11-24

Family

ID=14948815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12698679A Granted JPS5651682A (en) 1979-10-01 1979-10-01 Unnecessary-reflected-wave eliminator of radar device

Country Status (1)

Country Link
JP (1) JPS5651682A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2776032B2 (en) * 1991-02-08 1998-07-16 三菱電機株式会社 Target identification device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325780B2 (en) * 1974-07-29 1978-07-28
JPS53114651A (en) * 1977-03-17 1978-10-06 Fujitsu Ltd Electronic circuit

Also Published As

Publication number Publication date
JPS5651682A (en) 1981-05-09

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