JPS6364367A - Compound semiconductor field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a function as a compound semiconductor FET controlling load currents by forming a compound semiconductor layer for a channel layer shaping a channel layer in InxGa1-xAs (0<x<=1). CONSTITUTION:A compound semiconductor layer 21 for a buffer layer is inserted between a semi-insulating compound semiconductor substrate 1 and a compound semiconductor layer 2 for a channel layer. The compound semiconductor layer 2 for the channel layer is formed in InxGa1-xAs (O<x<=1). Consequently, the difference of energy levels between the bottom of a conduction band in the channel layer 2' and the bottom of a conduction band in a barrier layer 3' can be increased. Accordingly, even when control voltage is high, currents are not caused to flow through the gate layer 6 through the barrier layer 3' from the channel layer 2'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a compound semiconductor field effect transistor.

2. Description of the Related Art Conventionally, a compound semiconductor field effect transistor has been proposed as described below with reference to FIG.

That is, on one semi-insulating compound semiconductor substrate 1, an undoped compound semiconductor layer 2 for a channel layer, an undoped compound semiconductor layer q3 for a barrier layer, and an undoped compound semiconductor layer 4 for a cap layer. In that order, as a laminate 5, into a product? It is formed by i. In this case, the semi-insulating compound semiconductor substrate 1 is made of GaAS, the tunnel layer compound semiconductor layer 2 is made of GaAS, and the barrier layer compound semiconductor layer 3 is made of AI QaV 1-
V As (0<y≦1), and the cap layer compound semiconductor layer 4 is made of GaAS.

Thus, a gate layer semiconductor layer doped with n-type impurities at a relatively high temperature is locally formed as a gate layer 6 in a desired pattern on the stacked body 5 , and on each gate layer 6 . A gate electrode 7 is attached to. In this case, the gate layer 6 is made of Qe, and the gate electrodes 8!7 are made of tungsten silicide (WS'x).

In addition, in the uj body 5, from above and at both positions sandwiching the gate layer 6, semiconductor regions doped with n-type impurities at a high concentration are the compound semiconductor layer 2 for the channel layer and the compound semiconductor layer 2 for the barrier layer. The region between the semiconductor regions of the layer 3 and the compound semiconductor layer 4 for cap layer is formed into a channel layer 2, respectively.
', a barrier layer 3' and a cap layer 4' are formed as a source region 8 and a drain region 9 at a depth reaching the channel layer compound semiconductor layer 2, respectively. A source electrode tM10 and a drain electrode 11 are connected to each other from above.

The above is the ti4 structure of the conventionally proposed compound semiconductor field effect transistor.

According to the compound semiconductor field effect transistor having such a configuration, the source electrode 4410 and the drain electrode 11
In the meantime, if a necessary power source is connected through the load, and a control power source is connected between the gate electrode 7 and the source electrode 10, and the voltage of the III I211 power source is controlled, accordingly, The induction of two-dimensional electron gas is controlled on the barrier layer 3' side of the channel layer 2', and therefore the current flowing through the channel layer 2' between the source region 8 and the drain region 9 is controlled, and thus, A function as a compound semiconductor field effect transistor in which the current flowing to the n-charge is restricted is obtained.

Problems to be Solved by the Invention However, in the case of the conventional compound semiconductor field effect transistor shown in FIG.
Since the channel layer 2' is made of GaAS, the channel layer 2'
The energy level difference between the bottom of the conduction band of the barrier layer 3' and the bottom of the conduction band of the barrier layer 3' is relatively low.

Therefore, depending on the value of the control voltage that is sufficient to cause current to flow through the channel layer 2',
A current flows to the gate layer 6 side through the barrier layer 3'.

For this reason, the gm of the compound lightning field effect transistor decreases, making it impossible to achieve high performance.Furthermore, if this is to be avoided, the value of the control voltage will be limited. , was a negative point.

Further, in the case of the conventional compound semiconductor field effect transistor shown in FIG. 5, the barrier layer 3' is made of A1, Ga1□AS, whereas the gate layer 6 is made of Ge.
The energy level difference between the bottom of the conduction band of ' and the bottom of the conduction band of the gate layer 6 is the energy level difference between the bottom of the conduction band of the channel layer 2' and the bottom of the conduction band of the barrier layer 3'. This is large compared to the difference. For this reason, even if the function as a compound semiconductor field effect transistor can be obtained as an enhancement type transistor, it cannot be obtained as a depletion type transistor. Further, for this reason, the difference in energy level between the bottom of the conduction band of the barrier layer 3' and the bottom of the conduction band of the gate layer 6 is the same as that of the bottom of the conduction band of the channel layer 2' and the bottom of the conduction band of the barrier layer 3'. Even if the gate layer 6 is not constructed using a semiconductor that satisfies the fact that the energy level difference is small compared to the bottom of the conduction band of Considering that the layer compound semiconductor layer 2, the barrier layer compound semiconductor layer 3, and the thousand layer compound semiconductor layer 4 are formed on the semi-insulating compound semiconductor substrate 1 using an epitaxial growth method, it is extremely difficult. be.

By means of solving the problems, the present invention seeks to propose a novel compound semiconductor field effect transistor free of the above-mentioned drawbacks and difficulties.

The compound semiconductor field effect transistor according to the present invention has the following configuration similar to the conventional compound semiconductor field effect transistor described above in FIG.

That is, on a semi-insulating compound semiconductor substrate, an undoped compound semiconductor layer for a channel layer and an undoped compound semiconductor layer for a barrier layer are formed in order of f? A laminate including i-layers is formed.

Further, a gate layer semiconductor layer doped with an impurity giving a desired conductivity type is locally formed on the above-mentioned laminate as a gate layer, and a gate electrode is attached on the gate layer.

Furthermore, first and second semiconductor regions doped with an impurity material giving the same conductivity type as the gate layer are provided in the stacked body at both positions sandwiching the gate layer from above. The compound semiconductor layer for channel layer is reached so that the region between the first and second semiconductor regions of the compound semiconductor layer for channel layer and the barrier layer phase compound semiconductor layer is formed as a channel layer and a buffer layer, respectively. A source region and a drain region are respectively formed in the depth.

Further, a source electrode and a train electrode are connected to the source region and the drain region, respectively.

However, in the compound semiconductor field effect transistor according to the present invention, in the compound semiconductor field effect transistor having such a structure, the compound semiconductor layer for channel layer forming the channel layer is I
nGaAs
As (0<y≦1).

y i-y Function/Effect According to the compound semiconductor field effect transistor according to the present invention having such a configuration, it is different from the structure of the conventional compound semiconductor field effect transistor described above in FIG. The compound semiconductor layer for the channel layer forming the channel layer is made of in instead of being made of GaAS.
It has the same structure as the conventional compound semiconductor field effect transistor 1 shown above in FIG. 5, except that it is Qal-XAS (O<x≦1).

For this reason, as in the case of the conventional compound semiconductor field effect transistor described above in FIG. If the voltage of the 1ill t11 power supply is controlled while the power supply is connected, the induction of two-dimensional electron gas on the barrier layer side of the channel layer is controlled accordingly, and therefore the source region and drain region The ability of the compound semiconductor field effect transistor to control the current flowing through the channel layer in between, thereby controlling the current flowing to the load, is obtained.

However, in the case of the compound semiconductor field effect transistor according to the present invention, the barrier is Δ1°Ga1. Since the channel layer is made of InGaAS while the channel layer is made of As, the energy level difference between the bottom of the conduction band of the channel x 1-X and the bottom of the conduction band of the barrier layer is can be high for compound semiconductor field effect transistors. For this reason, in the conventional compound semiconductor field effect transistor described above in FIG. Therefore, no current flows through the barrier layer to the gate layer side. Therefore, there is less risk that high performance will not be obtained due to a decrease in gm of the compound semiconductor field effect transistor, etc.
Furthermore, the possible values of the control voltage are not greatly restricted.

Further, in the case of the compound semiconductor field effect transistor according to the present invention, the barrier layer is made of AI Ga1-.

As, the energy level difference between the bottom of the conduction band of the barrier layer and the bottom of the conduction band of the gate layer is expressed as the energy level difference between the bottom of the conduction band of the channel layer and the bottom of the conduction band of the barrier layer. It can be made smaller compared to the level difference. Therefore, the function as a compound semiconductor field effect transistor can be obtained in an enhancement type manner. Also, at this time, the gate layer is connected to Selecting a semiconductor that satisfies the fact that the energy level difference between It is extremely easy to form the semiconductor layer on a semi-insulating compound semiconductor substrate using an epitaxial growth method.

Example 1 Next, with reference to FIG. 1, a first example of a compound semiconductor field effect transistor according to the present invention! ,'I will state.

In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed explanation will be omitted.

The compound semiconductor field effect transistor according to the present invention shown in FIG. 1 has the same structure as the conventional compound semiconductor field effect transistor described above in FIG. 5, except for the following points.

That is, the buffer layer compound semiconductor layer 21 is interposed between the semi-insulating compound semiconductor substrate 1 and the channel layer compound semiconductor layer 2, and the channel layer compound semiconductor layer 2 is made of GaAs. Instead, InGa
As (0<x 1-x X≦1). In this case, the compound semiconductor layer 2 for channel layer (1nxGa1-xAS constituting it)
Let 1 shift of X be 0.45 and get 1.

The following is the structure of the first embodiment of the compound semiconductor field effect transistor according to the present invention.

According to the compound semiconductor field effect transistor according to the present invention having such a configuration, it has the same configuration as the conventional compound semiconductor field effect transistor described above in FIG. 5, except for the matters mentioned above. As in the case of the conventional compound semiconductor field effect transistor described above in FIG. 1] With the power supply connected, if you control the voltage of the control power supply,
The induction of two-dimensional electron gas is controlled on the barrier layer 3' side of the channel layer 2', and therefore the current flowing through the channel layer 2' between the source region 8 and the drain region 9 is controlled, and therefore the load This provides the ability of a compound semiconductor field effect transistor to control the current flowing through the transistor.

However, in the case of the compound semiconductor field effect transistor according to the invention shown in FIG. 1, the barrier 13' is A ly
Ga1-y AsT' (7) t, = On the other hand, the channel layer 2' is different from GaAs and is 1nQa A
s, the energy level difference between the bottom of the conduction band of the channel layer 2'x 1-x and the bottom of the conduction band of the barrier layer 3' is as shown in FIG. It can be made larger than that of conventional compound semiconductor field effect transistors.

Therefore, in the conventional compound semiconductor field effect transistor described above in FIG. Even if from the channel layer 2',
No current is allowed to flow through the barrier layer 3' to the gate layer 6 side. For this reason, compound semiconductor heavy yl! There is less risk that high performance will not be obtained due to a decrease in the gm of the effect transistor, and the control voltage
qru] There are no major restrictions on directness.

Further, in the case of the compound semiconductor 7z field effect transistor according to the present invention shown in FIG. 1, the barrier layer 3' is made of AtGa, -, as in the case of the conventional compound semiconductor field effect J-transistor described above in FIG. Even if the layer 6 is made of Ge, the difference in energy level between the bottom of the conduction band of the channel layer 2' and the bottom of the conduction band of the barrier layer 3' is as described above. In addition, since it can be made larger than that of the conventional compound semiconductor field effect transistor described above in FIG. 5, the bottom level of the conduction band of the barrier layer 3' can be lowered accordingly. Therefore, as shown in FIG. 2, the energy level difference between the bottom of the conduction band of the barrier layer 3' and the bottom of the conduction band of the channel layer 2' is expressed as The energy level difference between the barrier layer 13' and the bottom of the conduction band can be made smaller. Therefore, the function as a compound semiconductor field effect transistor can be made into a depression type transistor.

Of course, the gate layer 6 can be formed on the semi-insulating compound semiconductor substrate 1 together with the compound semiconductor layer 2 for the channel layer, the compound semiconductor layer 3 for the barrier layer, and the compound semiconductor layer 4 for the cap layer using an epitaxial growth method. can.

Furthermore, according to the compound semiconductor field effect transistor according to the present invention shown in FIG. 1, a compound semiconductor layer 2 for a channel layer forming a channel layer 2'. However, on the semi-insulating compound semiconductor substrate 1, a compound semiconductor layer 21 for barrier layer is formed.
Since the compound semiconductor layer 2 for the channel layer can be easily formed to a thinner thickness than when it is directly formed on the semi-insulating compound semiconductor substrate 1, , the compound semiconductor layer 2 for channel layer can be formed satisfactorily without misfit dislocations.

In addition, the value of
! ! As II is reached, the compound semiconductor layer 2 for the channel layer is lattice matched with the compound semiconductor layer 21 for the buffer layer and the semi-insulating compound semiconductor substrate 1 by increasing the size continuously or stepwise. can be formed.

Embodiment 2 Next, a second embodiment of the compound semiconductor field effect transistor according to the present invention will be described with reference to FIG.

In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The compound semiconductor field effect transistor according to the present invention shown in FIG. A drain region 9' similar to the one shown in FIG. , formed at a depth reaching the buffer layer compound semiconductor layer 21 to form the barrier layer 3'' and the cap layer 4'', and also on the source region 9'', corresponding to the drain electrode 11. A train electrode 11' is connected,
Further, on the stacked body 5, a source region 8 and a drain region 9 are provided.
The compound semiconductor field effect transistor according to the present invention as described above in FIG. It has a similar configuration.

The above is the configuration of the second embodiment of the compound semiconductor field effect transistor according to the present invention.

According to the compound semiconductor field effect transistor according to the present invention having such a configuration, it is similar to the compound semiconductor field effect transistor according to the present invention described above in FIG. 1, except for the matters mentioned above. The structure includes a semi-insulating compound semiconductor substrate 1, a buffer layer compound semiconductor layer 21, a source region 8 and a drain region 9, and a source electrode 1.
0, drain electrode 11, channel layer 2', barrier layer 3', cap layer 4', gate layer 6, and gate electrode 7 function as a depletion type compound semiconductor field effect transistor, as in the case of FIG. 11 can be done.

Further, the gate electrode 7' includes the gate layer 6 and the gate electrode 7.
Although a detailed explanation will be omitted since it corresponds to a laminate consisting of a semi-insulating compound semiconductor substrate 1, a barrier layer compound semiconductor layer 21, a source region 8 and a drain region 9', a source electrode 10 and a drain electrode 11. ', Channel FJ
7J2'', barrier layer 3'', cap layer 4'' and gate electrode 7', the performance of the compound semiconductor field effect transistor can be reduced (q).However, in this case, as shown in FIG. The energy level difference between the bottom of the conduction band of electrode 7' and the bottom of the conduction band of barrier layer 3'' is defined as the difference in energy level between the bottom of the conduction band of channel layer 2'' and the bottom of the conduction band of barrier layer 3''. Since the energy level difference can be made large compared to the energy level difference, the function as a compound semiconductor field effect transistor can be obtained in an enhancement type manner.

Therefore, it is possible to configure an inverter circuit using an enhancement type compound semiconductor field effect transistor as an input and a depletion type compound semiconductor field effect transistor as a load.

In the above description, J3 merely shows two embodiments of the present invention, and J3 has the structure described above in FIGS. 1 and 3, and the cap layer compound semiconductor layer 4 forming the cap layer is J omitted? It can also be made into four components.

Further, the semi-insulating compound semiconductor substrate 1 is made of InP, and accordingly, the compound semiconductor layer 21 for rose fluoride is made of InP.
is omitted, but the compound semiconductor layer 2 for the channel layer is formed to have a large thickness, or the compound semiconductor layer 21 for the buffer is lattice-matched to the semi-insulating compound semiconductor substrate 1 using InAIA.
It can also be made of an S-based semiconductor. In this case, the compound semiconductor layer 2 for the channel layer can be lattice-matched with the semi-insulating compound semiconductor substrate 1, and for this reason, the compound semiconductor layer 2 for the channel layer can be formed by (14). It is not necessarily necessary to increase the value of X of 1nQa As from the value of O on the side of the buffer layer compound X 1-x compound semiconductor layer 21 to the side of the compound semiconducting layer 3 for use as a base layer.

However, in this case, it is possible to form the barrier compound semiconductor layer 3 to a sufficiently thin thickness, such as 100 layers, which is sufficient to prevent misfit dislocations from occurring. Also, buff? Since the layer compound semiconductor layer 21 has a higher resistance than the channel layer compound semiconductor layer 2, leakage current is small.

Furthermore, in the case of FIG. 3, the gate electrode 7' is made of tungsten silicide, but the gate electrode 7'
can also be formed of other metals than tungsten silicide, and can also be formed of In2Ga 1. which is heavily doped with n-type impurities. ．． It can also be made of 7AS. In this case, the value of 2 is determined by the InxGa that forms the channel layer compound semiconductor layer 2
By setting the value of X to be larger than the value of can.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a compound semiconductor field effect transistor according to the present invention. Figures 2 A and B show the control voltage for the d2 brightness,
They are energy band diagrams when a value is set to allow current to flow through the load and when a value is set to a value that does not allow current to flow through the load, respectively. FIG. 3 is a cross-sectional view showing a second embodiment of a compound semiconductor field effect transistor according to the present invention. FIGS. 4A and 4B are energy band diagrams when the control voltage is set to a value that does not allow current to flow through the load and a value that allows current to flow through the load, respectively, for purposes of explanation. FIG. 5 is a cross-sectional view, not showing a conventional compound semiconductor field effect transistor. 1... Semi-insulating compound semiconductor substrate 2...
・・・・・・Compound semiconductor for channel layer]2
H, 2JT ...... Channel layer 3 ...... Compound semiconductor layer for barrier layer 3 r
, 3 rt...Barrier store 4...Compound semiconductor layer for cap layer 4'
, 4″ ...... Cap layer 5 ...... Laminated body 6 ...... Compound semiconductor layer for gate m 7.7
′......Gate electrode 8...Source region 9.9'...Drain region 10.11.11' 21... ...Buffer footwear compound semi-central body layer Applicant Nippon Telegraph and Telephone Corporation Agent Patent attorney 1) Masaharu Naka・■゛". Tsuba IN, 7 Figure 2 Figure 8 Figure 4

Claims (1)

[Claims] A laminate is formed on a semi-insulating compound semiconductor substrate, in which an undoped compound semiconductor layer for a channel layer and an undoped compound semiconductor layer for a barrier layer are laminated in that order, A semiconductor layer for a gate layer doped with an impurity giving a required conductivity type is locally formed on the body as a gate layer, a gate electrode is attached on the gate layer, and the semiconductor layer is formed in the stacked body. From above, at both positions sandwiching the gate layer, first and second semiconductor regions doped with an impurity giving the same conductivity type as the gate layer form the compound semiconductor layer for the channel layer and the compound semiconductor layer for the barrier layer. Form regions between the first and second semiconductor regions of the compound semiconductor layer as a channel layer and a buffer layer, respectively, to a depth reaching the compound semiconductor layer for channel layer as a source region and a drain region, respectively. In the compound semiconductor field effect transistor in which a source electrode and a drain electrode are connected to the source region and the drain region, respectively, the channel layer compound semiconductor layer forming the channel layer is formed of In_x
The barrier layer compound semiconductor layer forming the barrier layer is made of Ga_1_-_xAs (0<x≦1), and the barrier layer compound semiconductor layer forming the barrier layer is Al_yGa_1_-_yAs (0<y≦1).
A compound semiconductor field effect transistor characterized by: