JPS63643U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a power factor control device according to an embodiment of this invention, Fig. 2 is a hardware block diagram of the above embodiment, Fig. 3 is an internal program flow diagram of capacitor control command processing, and Fig. 4 is a block diagram of a power factor control device according to an embodiment of the invention. Flowchart of uncontrollable detection processing, Fig. 5 is a capacitor control scratch table diagram, Fig. 6 is a waveform diagram explaining control operation of 3-bank capacitor connection type, Fig. 7A,
B and C are waveform diagrams explaining three types of error states, FIG. 8 is a configuration diagram showing a conventional power factor control device, FIG. 9 is a waveform diagram explaining conventional control operation, and FIG.
The figure is an explanatory diagram of capacitor input combinations when a plurality of capacitors (3 capacitors) are connected. In the figure, 1 and 10 are power factor control devices, 2 is a reactive power value, 13 is an uncontrollable detection means, and 14 is a suppression switch. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] In a power factor control device that controls the input amount of a power factor improvement capacitor by comparing the detected reactive power value with the set value of the target range width, it is possible to detect an uncontrollable state if the power factor control operation continues for a predetermined time or longer. What is claimed is: 1. A power factor control device, comprising: an uncontrollable detection means that detects the power factor and sends out an alarm output and also sends out a suppression signal for power factor control operation.