JPS6365263B2 - - Google Patents

Description

[Detailed Description of the Invention] [Description of Technical Field] The present invention provides carrier synchronization and automatic gain control (hereinafter referred to as " AGC”
That's what it means. ) related to improvements.

[Description of prior art]

A multiphase PSK (especially 8-phase or more) type synchronous detection demodulator requires stable and accurate carrier wave recovery and automatic gain functions.

In conventional demodulators, the baseband processing type Costas loop (for example, Japanese Patent Application No. 156124/1984) is well known as a carrier wave regeneration method. However, this method has drawbacks such as a complicated circuit configuration, high power consumption, and troublesome adjustment.

Figure 1 shows a block diagram of a conventional 8PSK demodulator. This method is described in the aforementioned Japanese Patent Application No. 156124/1983. The intermediate frequency input IFIN is branched into two by the signal branching circuit 1, and its output is sent to the phase detector 2,
Enter 3. The output of the voltage controlled oscillator (hereinafter referred to as "VCO") 6 is branched into two by a signal branching circuit 5, and a π/2 phase shifter 4 is used on one side to give a π/2 phase shift, and then the phase detection 2 and 3 for orthogonal synchronous detection. The detection output is subjected to binary discrimination by binary discriminators 10 and 13, and the addition circuit 8 and subtraction circuit 9 calculate the sum and difference of the outputs.
The outputs of the addition circuit 8 and the subtraction circuit 9 are sent to the phase detector 2.
Signals equivalent to those obtained by synchronous detection using carrier phases that are phase-advanced by π/4 and 3π/4, respectively, with respect to the carrier phase that is being supplied are obtained. The outputs of the addition circuit 8 and the subtraction circuit 9 are respectively output to the binary discriminator 1.
Binary identification is performed with 1 and 12. Binary classifier 10-1
The output of No. 3 is subjected to code conversion and differential conversion by a code converter 14, and becomes final output data.

As the carrier synchronization method, the phase detectors 2 and 3
The outputs of the adder circuit 8 and the subtracter circuit 9 are guided to branch rectifiers 15 to 18 for full-wave rectification. moreover,
The outputs of the branching rectifiers 15 and 16 are sent to an adder circuit 19,
The outputs of the branching rectifiers 17 and 18 are summed by an adder circuit 20. The outputs of the adder circuits 19 and 20 are subtracted by a subtracter circuit 21. The four outputs of the binary discriminators 10 to 13 are exclusive ORed by an exclusive OR circuit 23. Depending on the result, the polarity of the signal from the subtraction circuit 21 is inverted by a switch 22, and automatic phase control (hereinafter referred to as "APG") for carrier synchronization is performed.
That's what it means. ) signal and passes through the low frequency converter 7.
Controls VCO6.

However, in this method, in order to perform analog processing on the outputs of four full-wave rectifiers, it is necessary to finely adjust the amplitude and DC balance of each rectifier output.
Adjustment man-hours increase. Also, this circuit is
Since it does not have this function, it requires a separate AGC circuit, which has the disadvantage of increasing the circuit scale.

[Explanation of purpose]

The present invention improves on this point, and aims to provide an inexpensive 8PSK demodulator that is easy to adjust, suitable for digital circuitry, has a small circuit scale, and has both AGC and APC functions. do.

[Summary of the invention]

The present invention includes a signal branching circuit into which an eight-phase phase modulated wave is input, a voltage controlled oscillator controlled by an automatic phase control signal for carrier synchronization, and an output signal of one of the signal branching circuits as an output of the voltage controlled oscillator. a first phase detector that performs orthogonal synchronous detection with the output signal of the other output signal of the signal branch circuit using the π/2 shifted output of the voltage controlled oscillator; an addition circuit for adding the output of the phase detector and the output of the second phase detector; a subtraction circuit for subtracting the output of the first phase detector and the output of the second phase detector; It comprises first and second phase detectors and first to fourth binary discriminators to which the outputs of the addition circuit and the subtraction circuit are respectively connected, and the outputs D ₁ , D ₂ , In an 8-phase phase demodulator that converts the codes of D ₄ and D ₃ , an automatic gain control circuit is placed before the signal branching circuit, and a first full-wave rectifier is used to perform full-wave rectification of the output of the first phase detection circuit. a second full-wave rectifier circuit that full-wave rectifies the output of the second phase detector, and a first full-wave rectifier circuit that generates an error signal _EPL in the x direction from the output of the first full-wave rectifier circuit. a second binary discriminator that generates a y-direction error signal E _PU from the output of the first full-wave rectifier circuit;
a third binary discriminator that generates an x-direction error signal E _QL from the output of the second full-wave rectifier circuit 8; and a y-direction error signal from the output of the second full-wave rectifier circuit.
A fourth _binary discriminator that generates E _{QU and} four _{Y P , Y Q ,}
circuit means for generating Y′ _P and Y′ _Q ; and signals Y _P and Y _Q of these four signals are subtracted from each other and supplied as a control signal for an automatic phase control circuit that controls the voltage controlled oscillator. and means for mutually adding the signals Y' _P and Y' _Q among the four signals to obtain the automatic phase control signal.

[Explanation based on examples]

An embodiment of the present invention will be described based on the drawings.
FIG. 2 is a block diagram of essential parts of an embodiment of the present invention. When compared with the conventional example shown in FIG. 1, it has the following features. That is, the full-wave rectifiers 15 and 16 are omitted, and the outputs of the full-wave rectifiers 17 and 18 are input to binary discriminators 24, 25 and 26, 2, respectively.
7, and this output is connected to the AND circuit 29~
30, respectively. Further, the outputs of the binary discriminators 11 and 12 are led to an exclusive OR circuit, and the outputs are led to the AND circuits 29 and 32, and the inverted outputs are sent to the AND circuits 30 and 31.
lead to. The outputs of the AND circuits 29 to 32 are led to the input terminals of OR circuits 34 and 35, respectively, the outputs are led to the adder circuit 36, the outputs are led to the AGC circuit 37, and the outputs are led to the signal branch circuit 1.

Further, the outputs of the OR circuits 34 and 35 are led to one input terminal of the exclusive OR circuits 39 and 40,
The outputs of the binary discriminator 10 are led to the input terminals of the exclusive OR circuits 39 and 41, respectively, and the outputs of the binary discriminator 13 are guided to the input terminals of the exclusive OR circuits 40 and 42, respectively. OR circuit 39, 40
The outputs of the exclusive OR circuits 42 and 41 are led to other input terminals, respectively, and
1 and 42 are respectively led to the subtraction circuit 43,
This output is guided to the low frequency converter 7.

Other points are similar to the conventional example shown in Fig. 1,
The same reference numerals indicate the same items.

With this circuit configuration, first, the intermediate frequency input signal IFIN enters the AGC circuit 37, is given a necessary gain, is branched by the signal branching circuit 1, and is input to the phase detectors 2 and 3. This phase detector 2,
3, one of the outputs obtained by branching the output of the VCO circuit 6 by the signal branching circuit 5, and the output shifted by π/2 by the π/2 phase shifter 4 are supplied to perform orthogonal synchronous detection. The output of the phase detector 2 is the binary discriminator 1
0, the output of the phase detector 3 is input to the binary discriminator 13 to obtain outputs D ₁ and D ₃ .

Further, the sum and difference of the outputs of the phase detectors 2 and 3 are calculated by an adder circuit 8 and a subtracter circuit 9, respectively.
The outputs of the addition circuit 8 and the subtraction circuit 9 are led to binary discriminators 11 and 12, respectively, and become D ₂ and D ₄ . _D1 ,
D ₂ , D ₃ , and D ₄ enter the code converter 14 and become three final data outputs.

Now, the outputs of the phase detectors 2 and 3 are input to two full-wave rectifier circuits 17 and 18, respectively. Here, the input (demodulated waveform) of the full-wave rectifier circuits 17 and 18
and the output waveform (full-wave rectified waveform) are shown in FIG.

Next, the output of the full-wave rectifier circuit 17 is output to a binary discriminator 2.
5 and 24, it is converted into digital signals E _PL and E _PU . The output of the full-wave rectifier circuit 18 is also converted into digital signals _EQL and _EQU using binary discriminators 27 and 26. The threshold values of E _PU ( _EQU ) and E _PL (E _QL ) are shown as α and β in Fig. 3.

Next, E _PU and E _QL are subjected to an operation using D ₂ D ₄ created by the exclusive OR circuit 33 and AND circuits 29 and 32. E _PL and E _QU are exclusive OR circuit 33
_{2 4} and AND circuits 30 and 31. Note that the symbols indicate exclusive OR, and the overline indicates an inverted signal (the same applies hereinafter). The outputs of AND circuits 29 and 30 are input to an OR circuit 34, and the outputs of AND circuits 31 and 32 are input to an OR circuit 35.
They become Y′ _P and Y′ _Q , respectively. Y′ _P and Y′ _Q are summed by an adder circuit 36 to control an AGC circuit 37 .

Next, Y' _P is operated with D ₁ and D ₂ using exclusive OR circuits 39 and 42, and Y' _Q is operated with D ₃ and D ₁ using exclusive OR circuits 40 and 41. The calculations are performed to yield Y _P and Y _Q , respectively. Y _P , Y _Q are subtraction circuits 43
The difference is taken at , and after noise is removed via a low-pass filter 7, the VCO circuit 6 is controlled to reproduce the carrier wave.

Here, FIG. 4 shows how to generate E _PU (E _QU ) and E _PL (E _QL ).

Further, FIG. 5 shows the waveforms of D ₁ , D ₂ , D ₃ , D ₄ , D ₂ D ₄ , and D ₁ D ₃ in the phase region (a ₁ to a ₃ ) of FIG. 6. D ₁ to _{D 4} are equivalent to synchronous detection using carrier waves having phases l ₁ to _{l 4} shown in FIG.

The principle of the present invention is that on the phase plane shown in FIG.
The phase region divided by l ₁ to _{l 4} at π/4 intervals is divided by two lines parallel to l ₁ and l ₃ (in Fig. 6) centered on the regular attraction point (marked with a circle in Fig. 6). , shown by the dashed line), and 4
The method is divided into two small areas, and generates error signal components in the _l1 direction (x direction) and _l3 direction (y direction) for each area, and generates control signals for both AGC and APC.

Here, Y′ _P = E _PU・(D ₂ D ₄ )+E _PL・( _{2 4} )…(1) Y′ _Q = E _QU・( _{2 4} )+E _QL・(D ₂ D ₄ )…(2) Y _P = Y′ _P D ₁ D ₃ …(3) Y _Q = Y′ _Q D ₁ D ₃ …(4), and (Y′ _P , Y′ _Q ) and (Y _P , Y _Q )
are shown in FIGS. 7 and 8, respectively.

The AGC function includes error signals (1, 1), (0,
Only the small area corresponding to (0) is valid, and the other (1,
0) and (0, 1) are erased by taking the sum and do not operate as control signals. As for the APC function,
Only the small areas corresponding to the error signals (1, 0) and (0, 1) are valid, and (0, 0) and (1, 1) disappear by taking the difference and do not operate as control signals.

In FIG. 8, the common phase deviation from the eight normal phase points is illustrated by the crosses, which generates a total (1,0) error signal in each region. It is clear that if the phase shift is taken in the opposite direction, an error signal of (0, 1) will be generated in each region. Therefore, if (Y _P −Y _Q ) is fed back to the VCO, the carrier wave can be regenerated.

In addition, the demodulated baseband signal of the 8PSK system is 4
However, there is a certain relationship between the two signals orthogonally detected by l ₁ and l ₃ . If we divide the four-value level into two parts: the outer large level (large level) and the inner small level (minor level), when one is a large level, the other must always be a small level. . This is a big difference from 16 (4×4) quadrature amplitude modulation (hereinafter referred to as "16QAM").

As is clear from equations (1) and (2), in the present invention, for example, when D ₂ D ₄ = 1, Y _P = E _PU ... large level detection Y _Q = E _PL ... small level detection, and 8PSK The difference between 16QAM and 16QAM is clearly incorporated into the calculation. As a result, the pseudo pull-in point ● (black circle) shown in FIG. 9 is completely eliminated, making stable demodulation operation possible. In FIG. 9, arrows indicate normal vector positions.

[Explanation of effects]

As described above, according to the present invention, it is possible to obtain an excellent and stable eight-phase phase demodulator that is easy to adjust, suitable for digital circuit implementation, and has a small circuit scale and power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a conventional example. FIG. 2 is a block diagram of essential parts of an embodiment of the present invention. FIG. 3 is a diagram showing demodulated waveforms and full-wave rectified waveforms. FIG. 4 is a diagram showing a method of generating an error signal. FIG. 5 is a diagram showing identification signals. FIG. 6 is a diagram showing the phase plane region division method. 7th
The figure shows the AGC signal layout. Figure 8 is an arrangement diagram of APC signals. FIG. 9 is a diagram showing a pseudo pull-in point using a normal error signal generation method. 1, 5...Signal branch circuit, 2, 3...Phase detector, 4...π/2 phase shifter, 6...VCO circuit, 7...Low frequency converter, 8, 19, 20, 36... ... Addition circuit, 9, 21 ... Subtraction circuit, 10 to 13, 24
~27... Binary discriminator, 14... Code converter, 1
5-18...Full wave rectifier.

Claims (1)

[Claims] 1. Signal branching circuit 1 into which 8-phase phase modulated waves are input
, a voltage controlled oscillator 6 controlled by an automatic phase control signal for carrier synchronization, and a first phase detector 2 that performs orthogonal synchronous detection of one output signal of the signal branch circuit 1 using the output of the voltage controlled oscillator 6. and a second phase detector 3 that orthogonally detects the other output signal of the signal branching circuit 1 using the π/2 shifted output of the voltage controlled oscillator 6; and the output of the first phase detector 2 and the an addition circuit 8 that adds the outputs of the second phase detector 3; a subtraction circuit 9 that subtracts the outputs of the first phase detector 2 and the second phase detector; and first to fourth binary discriminators 10, 11, 12, 13 to which the outputs of the adding circuit and the subtracting circuit 2, 8, 9, 3 are respectively connected, Outputs of discriminators 10, 11, 12, 13
In the 8-phase phase demodulator that converts the codes of D ₁ , D ₂ , D ₄ , and D ₃ , the output of the automatic gain control circuit 37 placed before the signal branching circuit 1 and the first phase detection circuit 2 a first full-wave rectifier circuit 17 that full-wave rectifies the output of the second phase detector 3; a second full-wave rectifier circuit 18 that full-wave rectifies the output of the second phase detector 3; and an output of the first full-wave rectifier circuit 17. A first binary discriminator 25 generates an error signal _EPL in the x direction from the output of the first full-wave rectifier circuit 17, and a second binary discriminator generates an error signal _EPU in the y direction from the output of the first full-wave rectifier circuit 17. 24
and a third binary discriminator 2 that generates an error signal E _QL in the x direction from the output of the second full-wave rectifier circuit 18.
7, and a fourth binary discriminator 2 that generates a y-direction error signal E _QU from the output of the second full-wave rectifier circuit 18.
6, and four from the above error signals E _PL , E _PU , E _QL , E _QU
circuit means for generating Y _P , Y _Q , Y' _P , Y'_Q; and automatic phase control for controlling the voltage controlled oscillator 6 by mutually subtracting the signals Y _P and Y _Q among these four signals. 8-phase, characterized in that it is provided with means for supplying it as a control signal for the circuit, and means for mutually adding the signals _Y'P and _Y'Q among the four signals to obtain the automatic phase control signal. Phase demodulator. However, the above four signals are Y′ _P = E _PU・(D ₂ D ₄ )+E _PL・( _{2 4} ) Y′ _Q = E _QU・( _{2 4} )+E _QL・(D ₂ D ₄ ) Y _P = Y′ _P D ₁ D ₃ Y _Q = Y′ _Q D ₁ D _3where , is exclusive OR.