JPS6365555A - Ready signal generating device - Google Patents

Abstract

PURPOSE:To execute a processing of a CPU at a high speed, and to prevent an abnormality processing by connecting and disconnecting a transfer to the CPU of a ready signal from a peripheral device, by a buffer circuit controlled by a control signal whose phase has lagged said signal. CONSTITUTION:It is supposed that option slots 1-3 have been allocated to a storage device. When a CPU 5 executes write and read to the storage device, a ready signal 4 sends out 'low' to the CPU 5 from the storage device and sets the CPU 5 to a waiting state, and during that time, the CPU 5 continues to wait until the ready signal 4 becomes 'high'. The storage device analyzes instructions of write and read, and sets the ready signal 4 to 'high', when it becomes a state that the next operation can be executed. The ready signal 4 is brought to a wired OR connection, therefore, it becomes the same terminal in the option slots 1-3, and as for a control signal bus, signals of the same terminal number are unified in each slot, therefore, wherever each storage device is placed in the option slots, the same operation can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic device including a CPU, an external storage device, and an input/output device.

[Conventional technology]

The CPU cannot operate until data transfer from peripheral storage circuits and input/output devices is completed, so a ready signal is required to remember whether data transfer has been completed. Conventionally,
As shown in FIG. 5, R1 of each device! ! A ready signal for cpσ104 was created by wired-OR connecting ADY signals 100 to 102 with an open collector gate.

[Problem that the invention seeks to solve]

However, in the prior art described above, the stray capacitance of one circuit is 1
03, the rise of the ready signal for CPH is slow, which causes malfunction. This is because it takes a certain amount of time for the floating capacitance 103 to be charged.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a device for creating a ready signal with sharp edges for CPH upon release.

[Means for solving problems]

The present invention is characterized by comprising means for buffering a ready signal from one peripheral device, and means for inputting a control signal delayed in phase from the ready signal to the means.

[Effect]

In the present invention, a three-state buffer or the like is used to control transmission of a ready signal from one peripheral device to the CPU.

[Implementation row]

The invention will be explained in detail below.

FIG. 1 is a block diagram illustrating the invention in detail.

Assume that option slots 1.2 and 3 are allocated to the tli device. Ready signal 4 is 1. C.P.
When US writes to and reads from storage,
Sends a low signal to C) σ5 from the storage device and places the CPU 5i in a waiting state. Meanwhile, the CPU 5 continues to wait until the ready signal 4 becomes high. The storage device parses and writes write and read commands.

Ready signal 4 when the next operation can be performed
get high. The ready signal 4, which performs the same operation and performs continuous access, is wired-OR connected, so that the option slots 1 to 3 have the same terminal. Since the control signal bus has unified signals with the same terminal number in each slot, each storage device can perform the same operation no matter where in the option slot it is placed.

Furthermore, the layout of control signals on the child circuit board can be easily performed.

FIG. 2 is a more detailed explanation of FIG. 1, in which three-state buffer control signals (hereinafter abbreviated as C3H7 signals) 21 to
4 to 26 are transmitted to CI'U5. Here, control signal 21 ~ B and ready signal 24 ~
The phase of 2G is determined by the circuit shown in Figure 3. When ready signals come from the converter 111 device inserted into the option slot, the rise of the ready signal is delayed by the flip frog 31, and the above-mentioned ready signal and AND are CON to be taken? The signal 21 becomes as shown in FIG.

Here, the time chart of FIG. 4 will be further explained as follows.

That is, time 1. When the processing for the storage device is finished and the ready signal rises, the C0NT signal 21 is low, so this signal becomes the signal n.Then, a little later, at time t1, the C0NT signal 21 rises. Pointed, R
1! IADY signal S and signal n are separated by the cutting blade, but at this time, due to the action of the resistance.

The level of signal n can be kept high.

〔Effect of the invention〕

As described in detail above, one aspect of the present invention is to transmit a ready signal from a peripheral device to a CPU.

Since the configuration is such that connection and disconnection are performed by a buffer circuit controlled by a control signal whose phase lags that of the signal,
Ready is quickly released for the CPU, and the CPU
It is possible to speed up processing and prevent abnormal processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the outline of the present invention, and FIG. 2 is a block diagram showing the outline of the present invention.
1 in more detail, FIG. 3 is a diagram showing a circuit array configuring a control signal whose phase is delayed from the ready signal, and FIG. 4 is a time chart showing the relationship between ready signal control signals, etc. FIG. 5 is a diagram showing a conventional ready signal control circuit.

Claims (1)

[Claims] means for buffering a ready signal from a peripheral device;
A ready signal generating device comprising means for inputting a control signal whose phase is delayed from the ready signal to the means.