JPS6367255U - - Google Patents
Info
- Publication number
- JPS6367255U JPS6367255U JP1986161236U JP16123686U JPS6367255U JP S6367255 U JPS6367255 U JP S6367255U JP 1986161236 U JP1986161236 U JP 1986161236U JP 16123686 U JP16123686 U JP 16123686U JP S6367255 U JPS6367255 U JP S6367255U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- heat spreaders
- groove
- power semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Description
第１図は本考案の一実施例の側断面図、第２図
は同実施例におけるチツプ搭載前の上面図、第３
図は従来例の側断面図、第４図は同従来例におけ
るチツプ搭載前の上面図、第５図は第４図の等価
回路図である。
１０：回路基板、３：電極パターン、４：入出
力端子、５：ヒートスプレツダー部、５ｂ：連結
部、５ｃ：溝、６：半導体チツプ。
Figure 1 is a side sectional view of one embodiment of the present invention, Figure 2 is a top view of the same embodiment before chip mounting, and Figure 3 is a side sectional view of an embodiment of the present invention.
4 is a top view of the conventional example before chip mounting, and FIG. 5 is an equivalent circuit diagram of FIG. 4. 10: circuit board, 3: electrode pattern, 4: input/output terminal, 5: heat spreader section, 5b: connecting section, 5c: groove, 6: semiconductor chip.
Claims (1)
半導体チツプが搭載されてなる電力半導体装置に
おいて、電気的に共通接続される上記ヒートスプ
レツダーを連結して一体化するとともに、該ヒー
トスプレツダーの連結部の下面に溝を設け、該溝
対応部分を通して基板上の一部配線パターンを形
成してなることを特徴とする電力半導体装置。 In a power semiconductor device in which a plurality of semiconductor chips are mounted on a substrate via heat spreaders, the heat spreaders that are electrically connected in common are connected and integrated, and the heat spreaders are 1. A power semiconductor device characterized in that a groove is provided on the lower surface of a connecting portion of a semiconductor device, and a part of a wiring pattern on a substrate is formed through a corresponding portion of the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986161236U JPH0442925Y2 (en) | 1986-10-21 | 1986-10-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986161236U JPH0442925Y2 (en) | 1986-10-21 | 1986-10-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6367255U true JPS6367255U (en) | 1988-05-06 |
| JPH0442925Y2 JPH0442925Y2 (en) | 1992-10-12 |
Family
ID=31087359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986161236U Expired JPH0442925Y2 (en) | 1986-10-21 | 1986-10-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442925Y2 (en) |
-
1986
- 1986-10-21 JP JP1986161236U patent/JPH0442925Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0442925Y2 (en) | 1992-10-12 |