JPS636741U - - Google Patents

Info

Publication number
JPS636741U
JPS636741U JP10029586U JP10029586U JPS636741U JP S636741 U JPS636741 U JP S636741U JP 10029586 U JP10029586 U JP 10029586U JP 10029586 U JP10029586 U JP 10029586U JP S636741 U JPS636741 U JP S636741U
Authority
JP
Japan
Prior art keywords
sealing
solder
pattern
circuit board
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10029586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10029586U priority Critical patent/JPS636741U/ja
Publication of JPS636741U publication Critical patent/JPS636741U/ja
Pending legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の膜回路基板を示す平面図、第
2図aは本考案においてセラミツクキヤツプと膜
回路基板とを組み合せた状態を示す断面図、bは
本考案のはんだ粒発生状況を示す平面図、第3図
aは従来例の膜回路基板を示す平面図、bはセラ
ミツクキヤツプを示す平面図、第4図aは従来に
おけるセラミツクキヤツプと膜回路基板とを組み
合せた状態を示す断面図、bは従来におけるはん
だ粒発生状況を示す平面図である。 1……シール用Auパターン、1a……拡大パ
ターン、2……膜回路基板、3……セラミツクキ
ヤツプ、4b……はんだ粒。
Fig. 1 is a plan view showing the membrane circuit board of the present invention, Fig. 2a is a sectional view showing a state in which the ceramic cap and the membrane circuit board are combined in the present invention, and Fig. 2 b shows the state of generation of solder particles in the present invention. FIG. 3A is a plan view showing a conventional membrane circuit board, FIG. 3B is a plan view showing a ceramic cap, and FIG. 4A is a sectional view showing a combination of a conventional ceramic cap and a membrane circuit board. , b are plan views showing the state of generation of solder grains in the prior art. 1...Au pattern for sealing, 1a...enlarged pattern, 2...membrane circuit board, 3...ceramic cap, 4b...solder grains.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツクキヤツプと膜回路基板との突き合せ
面にそれぞれ形成されたシール用Auパターン間
をはんだ付けにより接合して突き合せ部を気密封
止する構造において、前記シール用Auパターン
の一部に、余剰はんだを捕捉させる拡大パターン
を一体に形成したことを特徴とするはんだシール
用Auパターン。
In a structure in which sealing Au patterns formed on the abutting surfaces of a ceramic cap and a membrane circuit board are joined by soldering to hermetically seal the abutting portions, a portion of the sealing Au patterns is An Au pattern for a solder seal, characterized by integrally forming an enlarged pattern that traps solder.
JP10029586U 1986-06-30 1986-06-30 Pending JPS636741U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10029586U JPS636741U (en) 1986-06-30 1986-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10029586U JPS636741U (en) 1986-06-30 1986-06-30

Publications (1)

Publication Number Publication Date
JPS636741U true JPS636741U (en) 1988-01-18

Family

ID=30969983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10029586U Pending JPS636741U (en) 1986-06-30 1986-06-30

Country Status (1)

Country Link
JP (1) JPS636741U (en)

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