JPS636851A - Very thin semiconductor device - Google Patents

Very thin semiconductor device

Info

Publication number
JPS636851A
JPS636851A JP61150792A JP15079286A JPS636851A JP S636851 A JPS636851 A JP S636851A JP 61150792 A JP61150792 A JP 61150792A JP 15079286 A JP15079286 A JP 15079286A JP S636851 A JPS636851 A JP S636851A
Authority
JP
Japan
Prior art keywords
film
thickness
semiconductor element
semiconductor device
bump electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61150792A
Other languages
Japanese (ja)
Other versions
JPH0515306B2 (en
Inventor
Masayuki Arai
荒井 眞幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61150792A priority Critical patent/JPS636851A/en
Publication of JPS636851A publication Critical patent/JPS636851A/en
Publication of JPH0515306B2 publication Critical patent/JPH0515306B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To remove a pad electrode from the surface of an activated region and to enable the total thickness of a device to be determined only by a thickness of a semiconductor element, by forming the element so as to have a trapezoidal cross section and extending a bump electrode connecting conductor downwards to the surface of a film-type external lead. CONSTITUTION:In a very thin semiconductor device, a semiconductor element 1 has a trapezoidal cross section so that there is no pad electrode on the surface of the element 1 including an activated region. A passivation film 4 is therefore allowed to cover all the regions sufficiently, which eliminates the need of providing a thick molded coat. Further, since each conductor 2 for interconnecting the bump electrode is extended downwards along the inclined face of the element to the position of a film-type external lead 3, the total thickness of the device can be determined by the thickness of the element 1 itself.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はIcカード等の製造に適する超薄形構造の半導
体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device with an ultra-thin structure suitable for manufacturing IC cards and the like.

〔従来の技術〕[Conventional technology]

従来、この棟の薄形半導体装置はプリント基板に縦溝を
形成してこのなη・に半導体素子を収納するか、または
半導体素子を下向きにしてそのバンプ電極をプリント配
線に@後接続するかの何れかの手段によって作られてい
る。すなわち、半導体素子の形状には何等手を加えるこ
となくプリント基板への実装方法を工夫することによっ
てその実現がはからハている。
Conventionally, thin semiconductor devices of this type have either been made by forming a vertical groove on the printed circuit board and storing the semiconductor element in this groove, or by placing the semiconductor element facing downward and connecting its bump electrodes to the printed wiring. made by any of the following methods. In other words, this can be achieved by devising a mounting method on a printed circuit board without making any changes to the shape of the semiconductor element.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、前者のプリント基板内に半導体素子を収納する
構造のものでは約900pmの厚さとなり。
However, the former structure in which semiconductor elements are housed within a printed circuit board has a thickness of approximately 900 pm.

また、後者のプリント配憩へのバンク電極の直接接続構
造のものでも800μm程度にしか薄くはならないので
、このような実装方法の工夫のみでは、例えは最近提案
されているISO規格(案)0.76−厚のICカード
ft災実現るにはきわめて大きな困難が伴なう。
Furthermore, even with the latter structure in which the bank electrode is directly connected to the print distribution, the thickness can only be reduced to about 800 μm, so if only the devised mounting method is used, it will not be possible to meet the recently proposed ISO standard (draft) 0. .76-thick IC cards would be extremely difficult to implement.

不発明の目的は、上記の情況に鑑み、少くともICカー
ドの薄形化を容易に達成し得る超薄形半導体装1ft″
提供することでおる。
In view of the above circumstances, the object of the invention is to develop an ultra-thin semiconductor device with a thickness of 1 ft. that can easily achieve at least the thinning of an IC card.
By providing it.

〔問題点を解決するための手段〕[Means for solving problems]

不発明の超薄形半導体装置は、断面が台形形状の半導体
素子と、前記半導体素子の傾斜面に沿って設けられるバ
ンプ電極用配線導体と、前記バンプ電極用配線導体の先
端に接続されるフィルム状外部リード導体と、前記半導
体素子の活性化惟域を含む全表面を被覆するパグシベー
シ璽ン膜とを備えることを含む。
The uninvented ultra-thin semiconductor device includes a semiconductor element having a trapezoidal cross section, a bump electrode wiring conductor provided along an inclined surface of the semiconductor element, and a film connected to the tip of the bump electrode wiring conductor. The method further includes: a shaped external lead conductor; and a pagsi conductor coating covering the entire surface of the semiconductor device including the activation area.

かかる構造の半導体装置は、半導体素子の活性化領域を
含む面上にはパッド11弊が存在しないので、パックベ
ージ菖ン膜は活性化領域面は勿論アルミ配線および素子
の傾斜面に沿って設けられたバンプ電極用配線導体を含
むその他の全ての領域までも充分に被覆して厚膜のモー
ルド・コートを不要ならしめ、また、バンプ電極用配線
導体は素子の傾斜面に沿ってフィルム状外部リードの位
置まで充分下降しているので半導体装置全体の厚みは半
導体素子そのものの厚みでほぼ決定し得るようになる。
In a semiconductor device having such a structure, since the pad 11 does not exist on the surface including the active region of the semiconductor element, the packed base film is provided not only on the active region surface but also along the aluminum wiring and the inclined surface of the element. All other areas including the wiring conductor for bump electrodes are fully covered, eliminating the need for a thick mold coat. Since it is sufficiently lowered to the position of the leads, the thickness of the entire semiconductor device can almost be determined by the thickness of the semiconductor element itself.

従って、厚さ700pm以下の超薄形半導体装置が信頼
性を充分に保持してきわめて容易罠実現される。
Therefore, an ultra-thin semiconductor device with a thickness of 700 pm or less can be realized very easily while maintaining sufficient reliability.

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図(alおよび(blはそれぞれ不発明の一実施例
を示す断面図および平面図である。本実施例によれば本
発明の超薄形半導体装置は、断面が台形形状の半導体素
子1と、半導体素子1の傾斜面に沿って設けられたバン
プ電極用配線導体2と、このバンプ電極用配線導体2の
先端に接続されたフィルム状外部リード3と、半導体素
子1の活性化領域、アルミ配M(何れも図示しない)お
よびバンプ電極用配線導体2を含む全ての表面を被覆す
るよう形成されたバッジページ冒ン膜(窒化膜またはボ
リミイド樹脂膜)4とを含む。ここで、5はバンプ電極
用配線導体2とフィルム状外部リード3との接続部を強
固に固着する固着用衛脂、また、6はフィルム状外部リ
ード3t−被覆する絶縁フィルムでるる。
FIG. 1 (al and (bl) are a sectional view and a plan view, respectively, showing an embodiment of the invention. According to this embodiment, an ultra-thin semiconductor device of the present invention includes a semiconductor element 1 having a trapezoidal cross section. , a bump electrode wiring conductor 2 provided along the inclined surface of the semiconductor element 1 , a film-shaped external lead 3 connected to the tip of the bump electrode wiring conductor 2 , an activated region of the semiconductor element 1 , It includes an aluminum wiring M (none of which is shown) and a badge page coating film (nitride film or borimide resin film) 4 formed to cover all surfaces including the bump electrode wiring conductor 2.Here, 5 Numeral 6 denotes a sanitary adhesive for firmly fixing the connecting portion between the bump electrode wiring conductor 2 and the film-shaped external lead 3, and 6 denotes an insulating film that covers the film-shaped external lead 3t.

本実施例によると半導体装置全体の厚みは半導体素子l
の厚みで実質的に決定され、フィルム状外部リード3の
プリント基板との接続面を境として上下に分れる2つの
厚みhl、h2をそれぞれ等しく 300μm程度に抑
え込むことができる。すなわち、厚さが約600μmの
超薄形半導体装置を得ることができる。この厚さは現在
提案されているICカードのISO規格(案)の実現に
充分対応し得る数値である。
According to this embodiment, the thickness of the entire semiconductor device is the semiconductor element l
The two thicknesses hl and h2, which are vertically divided with the connection surface of the film-like external lead 3 to the printed circuit board as a border, can be suppressed to be equal to about 300 μm. That is, an ultra-thin semiconductor device with a thickness of about 600 μm can be obtained. This thickness is sufficient to meet the currently proposed ISO standard (draft) for IC cards.

第2図および第3図はそれぞれ不発明の他の実施例を示
す断面図である。すなわち、第2図は半導体素子1の活
性化領域面を下側に向けてプリント基板7の開口部上に
載置したものである。ここで、8はプリント基板7上の
プリント配線導体を示す。この構造は2つの厚みb3.
h4がそれぞれ400μm、3QQμmとなシ全体とし
ては700μm程度の厚みとなるが、EEILOM向き
となる。また、第3図は半導体素子lを薄膜のモールド
衛脂9で再被覆して信頼性を更に高めたものでるる。こ
の場合でも全体の厚みの増加は高々100μm程度に過
きないのでICカードの実装に大きな支障を与えること
はない。
FIGS. 2 and 3 are sectional views showing other embodiments of the invention. That is, in FIG. 2, the semiconductor element 1 is placed on the opening of the printed circuit board 7 with the active region surface facing downward. Here, 8 indicates a printed wiring conductor on the printed circuit board 7. This structure has two thicknesses b3.
When h4 is 400 μm and 3QQ μm, the total thickness is about 700 μm, which is suitable for EEILOM. Further, FIG. 3 shows a semiconductor device 1 recoated with a thin mold sanitizing agent 9 to further improve reliability. Even in this case, the increase in the overall thickness is only about 100 μm at most, so it does not pose a major problem in mounting the IC card.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、半導体1
子の断面を台形形状とすることにより文その活性化領域
面上からバット電極を取除き、またバンプ電極用配線導
体をフィルム状外部リード面まで下降せしめ得るので、
全体の厚さが半導体素子の厚みで一意的に定まル且つ信
頼性を向上させた半導体装置を容易に実現することがで
きる。
As explained in detail above, according to the present invention, the semiconductor 1
By making the cross section of the element trapezoidal, it is possible to remove the butt electrode from the surface of the activation region and to lower the wiring conductor for the bump electrode to the film-like external lead surface.
A semiconductor device whose overall thickness is uniquely determined by the thickness of the semiconductor element and whose reliability is improved can be easily realized.

すなわち半導体装置の超薄形化に顕著なる効果を奏し得
る。
In other words, a remarkable effect can be achieved in making the semiconductor device ultra-thin.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(alおよび(b)はそれぞれ本発明の一実施例
を示す断面図および平面図、第2図および第3図はそれ
ぞれ本発明の他の実施例を示す断面図でめる。 1・・・・・・半導体素子、2・・・・・・バンプ電極
用配線導体、3・・・・・・フィルムF外i!、l−ド
、4・旧・・パブシベーション膜、5・・・・・・固漸
用街脂、6・・・・・・絶縁フィルム、7・・・・・・
プリント基板、8・・・・・・プリント配線導体、9・
・・・・・モールド有脂s  hl * h2 a h
3mh4・・・・・・厚み。 第1図
Figures 1 (al and b) are a cross-sectional view and a plan view showing one embodiment of the present invention, respectively, and Figures 2 and 3 are cross-sectional views showing other embodiments of the present invention, respectively. ...Semiconductor element, 2...Wiring conductor for bump electrode, 3...Film F outside i!, L-do, 4.Old...Pubscivation film, 5・・・・・・Street grease, 6・・・Insulating film, 7・・・・・・
Printed circuit board, 8...Printed wiring conductor, 9.
...Mold fat s hl * h2 ah
3mh4...Thickness. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 断面が台形形状の半導体素子と、前記半導体素子の傾斜
面に沿って設けられるバンプ電極用配線導体と、前記バ
ンプ電極用配線導体の先端に接続されるフィルム状外部
リード導体と、前記半導体素子の活性化領域を含む全表
面を被覆するパッシベーシヨン膜とを備えることを特徴
とする超薄形半導体装置。
A semiconductor element having a trapezoidal cross section, a bump electrode wiring conductor provided along an inclined surface of the semiconductor element, a film-like external lead conductor connected to a tip of the bump electrode wiring conductor, and a semiconductor element having a trapezoidal cross section. An ultra-thin semiconductor device comprising: a passivation film covering the entire surface including an active region.
JP61150792A 1986-06-26 1986-06-26 Very thin semiconductor device Granted JPS636851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61150792A JPS636851A (en) 1986-06-26 1986-06-26 Very thin semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61150792A JPS636851A (en) 1986-06-26 1986-06-26 Very thin semiconductor device

Publications (2)

Publication Number Publication Date
JPS636851A true JPS636851A (en) 1988-01-12
JPH0515306B2 JPH0515306B2 (en) 1993-03-01

Family

ID=15504533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61150792A Granted JPS636851A (en) 1986-06-26 1986-06-26 Very thin semiconductor device

Country Status (1)

Country Link
JP (1) JPS636851A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091251A (en) * 1989-05-29 1992-02-25 Tomoegawa Paper Co., Ltd. Adhesive tapes and semiconductor devices
US5162945A (en) * 1989-06-27 1992-11-10 Asahi Kogaku Kogyo K.K. Ocular lens system
JP2004165188A (en) * 2002-11-08 2004-06-10 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2008053755A (en) * 2007-11-09 2008-03-06 Oki Electric Ind Co Ltd Semiconductor device and production method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091251A (en) * 1989-05-29 1992-02-25 Tomoegawa Paper Co., Ltd. Adhesive tapes and semiconductor devices
US5162945A (en) * 1989-06-27 1992-11-10 Asahi Kogaku Kogyo K.K. Ocular lens system
JP2004165188A (en) * 2002-11-08 2004-06-10 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2008053755A (en) * 2007-11-09 2008-03-06 Oki Electric Ind Co Ltd Semiconductor device and production method thereof

Also Published As

Publication number Publication date
JPH0515306B2 (en) 1993-03-01

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