JPS6377143A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6377143A
JPS6377143A JP22255186A JP22255186A JPS6377143A JP S6377143 A JPS6377143 A JP S6377143A JP 22255186 A JP22255186 A JP 22255186A JP 22255186 A JP22255186 A JP 22255186A JP S6377143 A JPS6377143 A JP S6377143A
Authority
JP
Japan
Prior art keywords
film
resistor
ions
implanted
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22255186A
Other languages
Japanese (ja)
Other versions
JPH0682787B2 (en
Inventor
Kazuhiro Kanbara
一博 神原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22255186A priority Critical patent/JPH0682787B2/en
Publication of JPS6377143A publication Critical patent/JPS6377143A/en
Publication of JPH0682787B2 publication Critical patent/JPH0682787B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To accurately obtain a high resistor by using a polycrystalline Si film for the resistor when many resistance elements are formed for an IC, implanting one conductivity type impurity ions, then implanting inert gas ions, and then not executing a heat treatment as it is. CONSTITUTION:The surface of an Si substrate 1 is covered with an SiO2 film 4, a recess is formed to match a desired resistor size, and a high purity polycrystalline Si film 3 is grown therein. Then, the film 3 is covered with an Si3N4 film 6, B<+> ions are implanted to the film 3, then heat treated at 1000 deg.C for 30 min to exchange the ions with Si atoms of crystal lattice point to be activated. Thereafter, this sheet resistor is measured, Ar<-> ions are implanted with reference to it. At this time, an accelerating voltage is set to 80% or less at the time of an impurity doping, the state that the crystal lattice remains broken by the Ar<-> ions remains without annealing, and used as a resistor. Thus, the irregularity of the resistance value is reduced to several %.

Description

【発明の詳細な説明】 [概要] 抵抗体とする多結晶シリコン膜に、一導電型不純物イオ
ンを注入して熱処理し、次いで、不活性ガスイオン、例
えば、窒素(N2)、酸素(02)、アルゴン(Ar)
などの不活性ガスイオンヲ注入し、未熱処理のままとす
る。このような抵抗体の形成方法は、抵抗値を一層精度
良く形成できる。
[Detailed Description of the Invention] [Summary] Impurity ions of one conductivity type are implanted into a polycrystalline silicon film to be used as a resistor, heat treated, and then inert gas ions such as nitrogen (N2) and oxygen (02) are implanted. , argon (Ar)
Injecting inert gas ions such as, etc., and leaving it unheated. This method of forming a resistor allows the resistance value to be formed with higher accuracy.

[産業上の利用分野] 本発明は半導体装置の製造方法に係り、特に、抵抗体の
形成方法の改善に関する。
[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a resistor.

XCやLSIのような半導体装置には、多数のトランジ
ス“り素子に多数の抵抗体(抵抗素子)が組み込まれて
、集積回路が構成されている。従って、半導体装置の品
質を高めるためには、高精度な抵抗値を有する抵抗体を
形成することが要望されている。
In semiconductor devices such as XC and LSI, many resistors (resistance elements) are incorporated into many transistor elements to form an integrated circuit. Therefore, in order to improve the quality of semiconductor devices, it is necessary to It is desired to form a resistor having a highly accurate resistance value.

[従来の技術] 従来、抵抗体は、半導体基板内に設けるベース領域の形
成と同時に抵抗体層を設ける形成方法等が知られている
が、基板内に抵抗体を設ける形成方法は数百にΩ程度の
高抵抗値をもった抵抗体を形成することが困難で、また
、多結晶シリコン膜を利用したセルファライン(自己整
合)による製造方法が採られるようになってきたために
、最近、半導体基板上に絶縁膜を介して被着した多結晶
シリコン膜を抵抗体層として形成する方法が用いられて
いる。
[Prior Art] Conventionally, a method for forming a resistor is known in which a resistor layer is formed at the same time as a base region is formed within a semiconductor substrate, but there are hundreds of methods for forming a resistor within a substrate. Recently, it has become difficult to form a resistor with a high resistance value on the order of Ω, and a manufacturing method based on self-alignment using polycrystalline silicon has come to be adopted. A method is used in which a polycrystalline silicon film is deposited on a substrate with an insulating film interposed therebetween as a resistor layer.

第3図はその多結晶シリコン膜からなる抵抗体の断面図
を示しており、1はシリコン基板、2はシリコン基板と
抵抗体との間に介在させた絶縁膜の酸化シリコン(Si
02)膜、3は抵抗体、4は抵抗体周囲を囲む5i02
膜、5は電極である。
FIG. 3 shows a cross-sectional view of the resistor made of the polycrystalline silicon film, where 1 is a silicon substrate and 2 is a silicon oxide (Si) insulating film interposed between the silicon substrate and the resistor.
02) Membrane, 3 is resistor, 4 is 5i02 surrounding the resistor
5 is an electrode.

第4図f8)〜(C1はその形成方法を示す工程順図で
、まず、同図(a)に示すように、シリコン基板1の表
面を熱酸化して、5i02膜2を生成し、その上に気相
成長(CVD)法で高純度の多結晶シリコン膜(例えば
、膜厚5000〜6000人)3を成長する。
Fig. 4f8) to (C1 are process diagrams showing the formation method. First, as shown in Fig. 4(a), the surface of the silicon substrate 1 is thermally oxidized to generate the 5i02 film 2, and then the 5i02 film 2 is formed. A high-purity polycrystalline silicon film 3 (eg, 5,000 to 6,000 thick) is grown thereon by vapor phase epitaxy (CVD).

次いで、同図(blに示すように、窒化シリコン(Si
2N3)膜6(膜厚1000人程度)をCVD法で被着
し、フォトプロセスによりパターンニングして、抵抗体
領域の多結晶シリコン膜部分のみを被覆したSi3N4
膜6を形成し、これをマスクにして露出した多結晶シリ
コン膜を熱酸化して5f02膜4を生成する。
Next, as shown in the same figure (bl), silicon nitride (Si
2N3) Si3N4 film 6 (film thickness of about 1000 layers) was deposited by CVD method and patterned by photo process to cover only the polycrystalline silicon film portion of the resistor region.
A film 6 is formed, and using this as a mask, the exposed polycrystalline silicon film is thermally oxidized to produce a 5f02 film 4.

次いで、第4図(C)に示すように、Si3N4膜6マ
スクの上から硼素または砒素をイオン注入し、更に、高
温度(約1000℃)で熱処理する。この熱処理は注入
イオンを結晶格子のシリコンと置換し、結晶格子点に硼
素または砒素を整置して、活性化するためである。しか
る後、Si3N4膜6を除去し、電極を形成して、第3
図のように完成する。
Next, as shown in FIG. 4(C), boron or arsenic ions are implanted from above the Si3N4 film 6 mask, and further heat treatment is performed at a high temperature (approximately 1000 DEG C.). This heat treatment is for replacing implanted ions with silicon in the crystal lattice, arranging boron or arsenic at crystal lattice points, and activating it. After that, the Si3N4 film 6 is removed, an electrode is formed, and the third
Complete as shown in the diagram.

[発明が解決しようとする問題点コ ところで、上記の形成工程において、硼素または砒素を
イオン注入して、高純度な多結晶シリコン膜をp型化、
あるいは、n型化するのは、多結晶シリコン膜のシート
抵抗を調整して、抵抗体が所望の抵抗値を持つようにす
るためである。これは、抵抗体の抵抗値が、周知のよう
に、長さ、断面積とシート抵抗によって決定されるから
である。
[Problems to be Solved by the Invention] By the way, in the above formation process, boron or arsenic ions are implanted to make the high purity polycrystalline silicon film p-type.
Alternatively, the purpose of making it n-type is to adjust the sheet resistance of the polycrystalline silicon film so that the resistor has a desired resistance value. This is because, as is well known, the resistance value of a resistor is determined by its length, cross-sectional area, and sheet resistance.

ところが、不純物イオンを注入し、シート抵抗を調整し
て、高精度な抵抗値を得ることは大変に難しく、且つ、
その再現性も良くない。特に、不純物の注入量を少なく
して、高シート抵抗を精度良く形成することが困難であ
る。それは、不純物濃度が低いほど、バラツキが増加す
るからである。
However, it is extremely difficult to obtain a highly accurate resistance value by implanting impurity ions and adjusting the sheet resistance.
The reproducibility is also not good. In particular, it is difficult to accurately form a high sheet resistance by reducing the amount of impurity implanted. This is because the lower the impurity concentration, the greater the variation.

本発明は、このような問題点を軽減させて、シート抵抗
を一層精度良く制御して、高精度な抵抗値をもった抵抗
体を形成する形成方法を提案するものである。
The present invention proposes a method of forming a resistor having a highly accurate resistance value by alleviating these problems and controlling the sheet resistance with more precision.

[問題点を解決するための手段] その目的は、絶縁膜上に設けた多結晶シリコン膜に、一
導電型不純物イオンを注入して熱処理し、次いで、不活
性ガスイオンを注入し、未熱処理のままとして、前記多
結晶シリコン膜を抵抗体に形成する形成方法によって達
成される。
[Means for solving the problem] The purpose is to implant impurity ions of one conductivity type into a polycrystalline silicon film provided on an insulating film, heat-treat the film, then implant inert gas ions, and then heat-treat the polycrystalline silicon film provided on the insulating film. This can be achieved by a method of forming the polycrystalline silicon film into a resistor as it is.

[作用] 即ち、本発明は、最初に、一導電型不純物イオンを注入
して熱処理し、次いで、窒素(N2 ) 。
[Operation] That is, in the present invention, impurity ions of one conductivity type are first implanted and heat treated, and then nitrogen (N2) is implanted.

酸素(02)、アルゴン(Ar)などの不活性ガスイオ
ンを注入し、未熱処理のままの抵抗体を形成する。そし
て、2回目の注入は1回目の注入によるシート抵抗の調
整にする。そうすると、抵抗値は一層精度良く制御でき
る。
Inert gas ions such as oxygen (02) and argon (Ar) are implanted to form a resistor without heat treatment. Then, the second injection is used to adjust the sheet resistance according to the first injection. In this way, the resistance value can be controlled with greater precision.

[実施例〕 以下、図面を参照して実施例によって詳細に説明する。[Example〕 Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(al、 (blは本発明にかかる形成方法の工
程順図を示しているが、従来の第3図(al、 (b)
で説明した、高純度な多結晶シリコン膜3を成長し、そ
の上にSi3N4膜6マスクを形成し、次に、熱酸化し
て5i02膜4を生成する工程は同一であるから図示し
ていない。次いで、第1図(a)に示すように、高純度
な多結晶シリコン膜からなる抵抗体3の上から硼素イオ
ン(p型不純物イオン)を注入する。その時、そのドー
ズ量は10″”7c+J、加速電圧100KeV程度に
する。そうして、次に、1000℃。
Figure 1 (al, (bl) shows the process order diagram of the forming method according to the present invention, while the conventional Figure 3 (al, (b)
The steps of growing a high-purity polycrystalline silicon film 3, forming a Si3N4 film 6 mask on it, and then thermally oxidizing it to generate a 5i02 film 4 are the same and are not shown in the figure. . Next, as shown in FIG. 1(a), boron ions (p-type impurity ions) are implanted from above the resistor 3 made of a high-purity polycrystalline silicon film. At that time, the dose is set to 10''7c+J and the acceleration voltage is set to about 100 KeV. Then, next, 1000℃.

30分間の熱処理をおこない、注入イオンを結晶格子点
のシリコン原子と置換して活性化する。その時、シート
抵抗(ρS)は数10Ωる 〜数にΩ4になり、そのシ
ート抵抗は測っておく。
Heat treatment is performed for 30 minutes to activate the implanted ions by replacing them with silicon atoms at crystal lattice points. At that time, the sheet resistance (ρS) will be several tens of Ω to several Ω4, and the sheet resistance will be measured.

次いで、第1図(blに示すように、シート抵抗(ρs
)を参照して、Arイオンを10 ” 〜1012/c
d程度のドーズ量で注入する。この時、加速電圧は1回
目の不純物のRpの80%以下にArのRpがくるよう
にする。且つ、その後の熱処理(アニール)はおこなわ
ないで、Arイオンで結晶格子が破壊されたままにする
。このようにして形成した抵抗体3のシート抵抗は、第
2図のシート抵抗(ρS)とドーズ量との関係図表に示
すように、ドーズ量に比例して微細に制御されたシート
抵抗(ρ3)が形成できる。
Next, as shown in Figure 1 (bl), the sheet resistance (ρs
), Ar ions are 10” to 1012/c
It is implanted at a dose of about d. At this time, the acceleration voltage is set so that the Rp of Ar is 80% or less of the Rp of the first impurity. Further, no subsequent heat treatment (annealing) is performed, and the crystal lattice is left destroyed by Ar ions. The sheet resistance of the resistor 3 formed in this way is finely controlled in proportion to the dose, as shown in the relationship chart between the sheet resistance (ρS) and the dose in FIG. ) can be formed.

なお、2回目のイオン注入の後、未熱処理とする理由は
、折角、高精度に制御したシート抵抗を変動させないよ
うにするためである。従って、このような抵抗体の形成
工程は、トランジスタ素子の形成工程と組み合わせる際
、以降に1000℃以上の熱処理がなされない工程位置
、例えば、エミッタ領域形成工程後に2回目のイオン注
入工程を挿入する必要がある。これに対して、1回目の
イオン注入工程はそのような制約がなく、適宜に挿入し
て良い。
Note that the reason why no heat treatment is performed after the second ion implantation is to prevent the sheet resistance, which has been carefully controlled with high precision, from changing. Therefore, when the process of forming such a resistor is combined with the process of forming a transistor element, a second ion implantation process is inserted at a process location where no subsequent heat treatment of 1000° C. or higher is performed, for example, after the emitter region formation process. There is a need. On the other hand, the first ion implantation step has no such restrictions and may be inserted as appropriate.

上記のような形成方法を採れば、数百にΩ程度の高い抵
抗値を高精度に形成でき、従来、抵抗値のバラツキが±
10%であったものは、数%のバラツキに低下させるこ
とが可能になる。
If the above formation method is adopted, high resistance values of several hundred ohms can be formed with high precision, and conventional variations in resistance values can be reduced to ±
What used to be 10% can now be reduced to a few percent variation.

且つ、不活性ガスイオンとして上記例のアルゴン(Ar
)の他、窒素(N2)、酸素(02)などの不純物ガス
イオンが考えられる。
In addition, as the inert gas ion, argon (Ar
), impurity gas ions such as nitrogen (N2) and oxygen (02) can be considered.

[発明の効果] 以上の実施例の説明から明らかなように、本発明によれ
ば高抵抗体を精度良く形成でき、ICの高品質化に大い
に寄与するものである。
[Effects of the Invention] As is clear from the description of the embodiments above, according to the present invention, a high-resistance element can be formed with high precision, which greatly contributes to improving the quality of ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、 (b)は本発明にかかる形成方法の工
程順図、 第2図はドーズ量とシート抵抗との関係図表、第3図は
多結晶シリコン抵抗体の断面図、第4図(5)〜(C)
は従来の形成方法の工程順図である。 図において、 ■はシリコン基板、  2.4は5i02膜、3は多結
晶シリコン膜からなる抵抗体、6はSi3N4膜 を示している。 Ar−Ay− オ発叶;〃・〃・3乃八゛かに−1ネ珈第1図 → トースパ1【 g−ズ(話とシーt−jbMてりnりf蚤〜7表第2図
1(a) and 1(b) are step-by-step diagrams of the formation method according to the present invention, FIG. 2 is a graph showing the relationship between dose and sheet resistance, and FIG. 3 is a cross-sectional view of a polycrystalline silicon resistor. Figure 4 (5) to (C)
1 is a step-by-step diagram of a conventional forming method. In the figure, (2) is a silicon substrate, 2.4 is a 5i02 film, 3 is a resistor made of a polycrystalline silicon film, and 6 is a Si3N4 film. Ar-Ay- O departure leaf; figure

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜上に設けた多結晶シリコン膜に、一導電型不純物
イオンを注入して熱処理し、次いで、不活性ガスイオン
を注入し、未熱処理のままとして、前記多結晶シリコン
膜を抵抗体に形成する工程が含まれてなることを特徴と
する半導体装置の製造方法。
Impurity ions of one conductivity type are implanted into the polycrystalline silicon film provided on the insulating film and heat treated, and then inert gas ions are implanted and the polycrystalline silicon film is formed into a resistor while left unheated. 1. A method for manufacturing a semiconductor device, comprising the steps of:
JP22255186A 1986-09-19 1986-09-19 Method for manufacturing semiconductor device Expired - Lifetime JPH0682787B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22255186A JPH0682787B2 (en) 1986-09-19 1986-09-19 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22255186A JPH0682787B2 (en) 1986-09-19 1986-09-19 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6377143A true JPS6377143A (en) 1988-04-07
JPH0682787B2 JPH0682787B2 (en) 1994-10-19

Family

ID=16784218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22255186A Expired - Lifetime JPH0682787B2 (en) 1986-09-19 1986-09-19 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0682787B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008536110A (en) * 2005-03-23 2008-09-04 ハネウェル・インターナショナル・インコーポレーテッド Polymer pressure sensor with piezoresistive region by injection
JP2014197701A (en) * 2008-09-25 2014-10-16 株式会社半導体エネルギー研究所 Semiconductor device manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008536110A (en) * 2005-03-23 2008-09-04 ハネウェル・インターナショナル・インコーポレーテッド Polymer pressure sensor with piezoresistive region by injection
JP2014197701A (en) * 2008-09-25 2014-10-16 株式会社半導体エネルギー研究所 Semiconductor device manufacturing method
US9960116B2 (en) 2008-09-25 2018-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0682787B2 (en) 1994-10-19

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