JPS6380687A - Cyclic type noise reducing device - Google Patents
Cyclic type noise reducing deviceInfo
- Publication number
- JPS6380687A JPS6380687A JP61225322A JP22532286A JPS6380687A JP S6380687 A JPS6380687 A JP S6380687A JP 61225322 A JP61225322 A JP 61225322A JP 22532286 A JP22532286 A JP 22532286A JP S6380687 A JPS6380687 A JP S6380687A
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- component
- noise
- input video
- amplitude limiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Television Signal Processing For Recording (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
この発明は、画像の動きを損なうことなく雑音低減の効
果を挙げるようにした巡回型雑音低減装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cyclic noise reduction device that achieves a noise reduction effect without impairing the motion of an image.
[従来の技術]
家庭用に用いられるビデオテープレコーダ等の磁気記録
再生装置は、周波数が高くなるほど増加する周波数塵・
復調方式に特有の三角雑音を取り除くため、一般には、
輝度信号を周波数変調する前にプリエンファシス回路に
より高域成分を強調しておき、信号再生時にディエンフ
ァシス回路により高域強調を解除することで、輝度信号
中の雑音を低減する方法を採っている。[Prior Art] Magnetic recording and reproducing devices such as video tape recorders used for home use are subject to frequency dust and dirt, which increases as the frequency increases.
In order to remove the triangular noise peculiar to the demodulation method, generally
A method is used to reduce noise in the luminance signal by emphasizing high-frequency components using a pre-emphasis circuit before frequency modulating the luminance signal, and canceling the high-frequency emphasis using a de-emphasis circuit during signal reproduction. .
しかし、ディエンファシス回路を経た輝度信号にも雑音
が含まれるため、例えば第3図に示す巡回型雑音低減装
置lを、磁気記録再生回路の再生出力端子lOに接続す
ることがある。図示の巡回型雑音低減装置lは、フィー
ルド又はフレーム相関の高い映像信号と、これらの相関
がほとんどない雑音成分との性質の違いを利用し、雑音
成分を抑圧するものであり、出力映像信号Vo (t)
を遅延して巡回的に入力映像信号Vi (t)に加算す
るため、巡回型の呼び名がある。入力映像信号Vi(t
)は、係数が1−にの係数42を介して加算器3に供給
される。そして、加算器3からは、人力映像信号に含ま
れる雑音を低減した出力映像信号Vo (t)が取り出
される一方、lフィールド周期又はlフレーム周期分の
信号遅延のため、遅延器4への供給が並行して行われる
。遅延時間がτの遅延器4を通過することで得られた遅
延出力映像信号Vo (を−τ)は、さらに係数器2の
係数1−にとはlの補数の関係にある係数Kをもつ係数
器5を通過することで、KVo(を−で)として前記加
算器3に供給され、そこで入力映像信号Vi (t)に
加算される。However, since the luminance signal that has passed through the de-emphasis circuit also contains noise, for example, a cyclic noise reduction device l shown in FIG. 3 may be connected to the reproduction output terminal lO of the magnetic recording and reproduction circuit. The illustrated cyclic noise reduction device 1 suppresses noise components by utilizing the difference in properties between a video signal with a high field or frame correlation and a noise component with little correlation between them, and reduces the output video signal Vo. (t)
It is called a cyclic type because it is delayed and cyclically added to the input video signal Vi (t). Input video signal Vi(t
) is supplied to the adder 3 via the coefficient 42 whose coefficient is 1-. Then, from the adder 3, an output video signal Vo (t) with reduced noise included in the human-powered video signal is taken out, while being supplied to the delay device 4 due to a signal delay of l field period or l frame period. are carried out in parallel. The delayed output video signal Vo (-τ) obtained by passing through the delay unit 4 with a delay time τ further has a coefficient K which is in the complement of l relationship with the coefficient 1- of the coefficient unit 2. By passing through the coefficient unit 5, it is supplied as KVo (with -) to the adder 3, where it is added to the input video signal Vi (t).
従って、出力映像信号Vo (t)は、(1−K)Vi
(t)+KVo (t−r)で表され、入力映像信号
Vi (t)と遅延出力映像信号Vo(t−τ)とに、
合算値が1となる相捕的な係数1−にとKを乗じた信号
の和が、出力映像信号Vo (t)となる。Therefore, the output video signal Vo (t) is (1-K)Vi
(t)+KVo (t-r), and between the input video signal Vi (t) and the delayed output video signal Vo(t-τ),
The sum of the signals obtained by multiplying the complementary coefficient 1- and K so that the sum value becomes 1 becomes the output video signal Vo (t).
[発明が解決しようとする間層点]
上記従来の巡回型雑音低減装置1は、係数器5の係数K
をlに近付け、相関をとる対象となるフィールド数又は
フレーム数を増やすほど、高いSN改善度が得られるこ
とが判っているが、係数器5の係数Kを1に近付けるほ
ど、SN改善度が向上する反面、相関をとる対象となる
フレーム数も多くなるため、動きの速い動画に対しては
残像が目立ってしまうといった弊害が生ずる問題があっ
た。[Interlayer points to be solved by the invention] The conventional cyclic noise reduction device 1 described above has a coefficient K of the coefficient multiplier 5.
It is known that the closer the coefficient K of the coefficient unit 5 is to 1 and the greater the number of fields or frames to be correlated, the higher the SN improvement can be obtained. Although this is an improvement, since the number of frames to be correlated increases, there is a problem in that afterimages become noticeable for fast-moving videos.
そこで、この種の残像問題を解消するため、例えば入力
映像信号Vi(t)と遅延出力映像信号Vo (t−τ
)との差信号が、動画になるほど信号レベルが大となる
ことに着目し、この差信号を検出して動作する動き検出
器により、残像が目立つような動画についてだけ、係数
にの値を小さな値に切り替えるといった対策をとる巡回
型雑音低減装置が提案された。しかし、このものは、動
き検出器が、差信号を形成するための減算器と減算器の
出力の絶対値をとる絶対値回路及び絶対値回路の出力を
あらかじめ設定した基準値と大小比較する比較回路等か
ら構成されるため、構成が複雑であり、製造コストが高
くつく等の問題点があった。Therefore, in order to solve this kind of afterimage problem, for example, input video signal Vi (t) and delayed output video signal Vo (t-τ
), we focused on the fact that the signal level of the difference signal becomes higher as the video becomes larger, and a motion detector that operates by detecting this difference signal reduces the value of the coefficient only for videos with noticeable afterimages. A cyclic noise reduction device has been proposed that takes measures such as switching to a value. However, this type of motion detector uses a subtracter to form a difference signal, an absolute value circuit that takes the absolute value of the output of the subtracter, and a comparison that compares the output of the absolute value circuit with a preset reference value. Since it is composed of circuits and the like, it has a complicated structure and has problems such as high manufacturing costs.
[問題点を解決するための手段]
この発明は、上記問題点を解決したものであり、AD変
換器とDA変換器が前後に接続された遅延用ディジタル
メモリからなる遅延器により、1フイ一ルド期間にもっ
とも近い整数ライン期間又はlフレーム期間だけ遅延し
た映像信号を、遅延前の映像信号に適宜の比率でもって
加算し、続いて前記遅延器による遅延に供することで、
映像信号中の信号成分と異なりフィールド相関又はフレ
ーム相関をもたない雑音成分を巡回的に低減する巡回型
雑音低減器と、この巡回型雑音低減器への入力映像信号
から出力映像信号を減算する第1の減算器と、この第1
の減算器の出力を振幅制限する振幅制限回路と、この振
幅制限回路の出力を前記入力映像信号から減算する第2
の減算器とを設けて構成したことを特徴とするものであ
る。[Means for Solving the Problems] This invention solves the above problems, and uses a delay device consisting of a delay digital memory in which an AD converter and a DA converter are connected in front and behind each other. By adding the video signal delayed by an integer line period or l frame period closest to the lead period to the video signal before delay at an appropriate ratio, and then subjecting it to delay by the delay device,
A cyclic noise reducer that cyclically reduces noise components that have no field correlation or frame correlation unlike signal components in a video signal, and subtracts an output video signal from an input video signal to the cyclic noise reducer. a first subtractor;
an amplitude limiting circuit that limits the amplitude of the output of the subtracter; and a second amplitude limiting circuit that subtracts the output of the amplitude limiting circuit from the input video signal.
The present invention is characterized in that it is configured by providing a subtracter.
[作用コ
この発明は、巡回型雑音低減により得られた出力映像信
号を、入力映像信号から減算することにより、入力映像
信号中の雑音成分と動画成分を抽出し、動画成分につい
て一定の振幅制限を施したのち、再び入力映像信号から
減算することで、雑音成分の除去と残像効果の抑制を図
る。[Operation] This invention extracts the noise component and the video component in the input video signal by subtracting the output video signal obtained by cyclic noise reduction from the input video signal, and applies a certain amplitude limit to the video component. After that, subtraction is performed again from the input video signal to remove noise components and suppress the afterimage effect.
[実施例コ
以下、この発明の実施例について、第1.2図を参照し
て説明する。第1図は、この発明の巡回型雑音低減装置
の一実施例を示す回路構成図である。[Example 7] Examples of the present invention will be described below with reference to FIG. 1.2. FIG. 1 is a circuit diagram showing an embodiment of a cyclic noise reduction device of the present invention.
第1図中、巡回型雑音低減装置11は、従来の遅延器4
に代え、遅延用ディジタルメモ川2の前後にAD変換器
13とDA変換器14を配した遅延器20を用いること
で、フィールド相関又はフレーム相関をとる上で重要な
遅延時間が正確に管理できるようにした巡回型雑音低減
器15を核に構成しである。遅延用ディジタルメモリ1
2は、■フィールド期間にもっとも近い整数ライン期間
、すなわち262ライン期間か263ライン期間又はl
フレーム期間を遅延時間にもつ。In FIG. 1, a cyclic noise reduction device 11 is a conventional delay device 4.
Instead, by using a delay device 20 in which an AD converter 13 and a DA converter 14 are placed before and after the delay digital memo 2, the delay time, which is important in taking field correlation or frame correlation, can be accurately managed. The structure is based on the cyclic noise reducer 15 as described above. Delay digital memory 1
2 is the nearest integer line period to the field period, i.e. 262 line period or 263 line period or l
The delay time is the frame period.
しかして、上記巡回型雑音低減器15は、入力映像信号
Vi(t)に含まれる雑音成分と動画成分を抽出するた
めの前処理回路としての機能に重点を置いたものであり
、そこから得られる出力映像信号Vo (t)は、第1
の減算器16に供給され、そこで入力映像信号Vi (
t)から減算されることで、入力映像信号Vi(t)に
含まれる雑音成分と動画成分の抽出に供される。Therefore, the cyclic noise reducer 15 focuses on the function as a pre-processing circuit for extracting the noise component and the moving image component contained in the input video signal Vi(t), and the function of the pre-processing circuit is The output video signal Vo (t) is the first
The input video signal Vi (
t) to extract the noise component and moving image component contained in the input video signal Vi(t).
ここで、第1の減算器16の出力に含まれる雑音成分と
動画成分は、続く振幅制限回路17にて、雑音成分の振
幅以下の成分を残して、他は振幅制限される。この振幅
制限回路17は、入力映像信号Vi(t)に含まれてい
た雑音成分と動画成分要部を抽出するためのものであり
、その振幅制限レベルは、外付けの可変抵抗Rvの抵抗
値に応じて、随意可変とされている。振幅制限回路17
にて得られた雑音成分と動画成分要部は、第2の減算器
I8にて、入力映像信号Vi(t)から減算され、ここ
ではじめて最終的な出力映像信号が得られることになる
。Here, the noise component and the moving image component included in the output of the first subtractor 16 are subjected to amplitude limitation in the following amplitude limiting circuit 17, leaving only the components whose amplitude is less than the amplitude of the noise component. This amplitude limiting circuit 17 is for extracting the noise component and the main part of the moving image component contained in the input video signal Vi(t), and its amplitude limiting level is determined by the resistance value of the external variable resistor Rv. It is said that it can be changed arbitrarily depending on the situation. Amplitude limiting circuit 17
The noise component and the main part of the moving image component obtained in step 1 are subtracted from the input video signal Vi(t) by the second subtractor I8, and only then is the final output video signal obtained.
すなわち、第2の減算器18から得られる最終的な出力
映像信号と、巡回型雑音低減器15から得られる出力映
像信号Vo (t)を比較した場合、当初の低減対象で
ある雑音成分については、はぼ対等の低減効果が見られ
る一方、動画成分については、明らかに最終的な出力映
像信号の方が抑制されており、これにより従来問題とさ
れた巡回型雑音低減に付随する残像効果の抑制が実現さ
れることが判る。That is, when comparing the final output video signal obtained from the second subtractor 18 and the output video signal Vo (t) obtained from the cyclic noise reducer 15, the noise component that is initially targeted for reduction is , while a comparable reduction effect can be seen, the final output video signal is clearly suppressed for the video component, and this eliminates the afterimage effect associated with cyclic noise reduction, which has been a problem in the past. It can be seen that suppression is achieved.
このように、巡回型雑音低減器rtttは、遅延用ディ
ジタルメモリ12からなる遅延器20を用いた雑音低減
能力の高い巡回型雑音低減器15から得られる出力映像
信号Vo (t)を、人力映像信号Vi(t)から減算
することにより、入力映像信号Vi(t)中の雑音成分
と動画成分を抽出し、続く振幅制限回路17にて動画成
分について一定の振幅制限を施したのち、再び入力映像
信号Vi(t)から減算することで、雑音成分の除去と
残像効果の抑制を図る構成としたから、従来の動き検出
器のような複雑な回路を用いることなく、2個の減算器
16.18と振幅制限回路17を1個用意することで、
動き検出器と同等の効果を挙げることができ、これによ
り装置全体の製造コストを低減し、しかも高品位の雑音
低減効果を挙げることができる。In this way, the recursive noise reducer rttt converts the output video signal Vo (t) obtained from the recursive noise reducer 15 having a high noise reduction ability using the delay device 20 consisting of the delay digital memory 12 into a human-powered video signal. The noise component and the moving image component in the input video signal Vi(t) are extracted by subtraction from the signal Vi(t), and after applying a certain amplitude limit to the moving image component in the subsequent amplitude limiting circuit 17, the input video signal is inputted again. By subtracting from the video signal Vi(t), the configuration aims to remove noise components and suppress afterimage effects, so two subtracters 16 can be used without using a complicated circuit like a conventional motion detector. By preparing .18 and one amplitude limiting circuit 17,
It is possible to achieve the same effect as a motion detector, thereby reducing the manufacturing cost of the entire device and achieving a high-quality noise reduction effect.
なお、振幅制限回路I7は、可変抵抗Rvにより振幅制
限レベルを随意可変できるので、人力映像信号Vi(t
)に含まれる雑音成分の程度に応じて振幅制限レベルを
可変することで、巡回型雑音低減により低減できる雑音
成分とこれと同レベルの動画成分だけを残すようにして
、不要な動画成分を取り除くことが可能であり、残像抑
制を図ったために雑音低減の効果が薄れるといった不都
合を、最大限押さえ込むことができる。Note that the amplitude limiting circuit I7 can arbitrarily vary the amplitude limiting level using the variable resistor Rv, so that the human video signal Vi(t
) By varying the amplitude restriction level according to the degree of noise components included in the noise component, unnecessary video components are removed by leaving only the noise components that can be reduced by cyclic noise reduction and the video components at the same level. This makes it possible to minimize the inconvenience that the effect of noise reduction is weakened due to afterimage suppression.
なお、巡回型雑音低減器15とは構成が若干界なるが、
基本原理が同じ巡回型雑音低減器25を用いることで、
第2図に示す巡回型雑音低減装置2Iを構成することも
可能である。この巡回型雑音低減装置21は、入力映像
信号Vj (t)から減算器22にて遅延出力映像信号
Vo(を−τ)を減算し、減算結果δV (t)に係数
器23にて係数Kを乗じ、係数器23の出力にδV (
t)をさらに減算器24にて入力映像信号Vi (t)
から減算することで、出力映像信号Vo (t)を得る
ものである。この巡回型雑音低減器25は、2個の減算
器22.24を用いたことで、入力映像信号Vi(t)
と遅延出力映像信号Vo(を−で)に乗算する相補的な
係数1−にとKが、単一の係数器23にて可能となる。Although the configuration is slightly different from that of the cyclic noise reducer 15,
By using the cyclic noise reducer 25 with the same basic principle,
It is also possible to configure a cyclic noise reduction device 2I shown in FIG. This cyclic noise reduction device 21 uses a subtracter 22 to subtract the delayed output video signal Vo (-τ) from the input video signal Vj (t), and adds a coefficient K to the subtraction result δV (t) using a coefficient multiplier 23. The output of the coefficient unit 23 is multiplied by δV (
t) is further inputted to the input video signal Vi (t) by the subtracter 24.
By subtracting from , the output video signal Vo (t) is obtained. This cyclic noise reducer 25 uses two subtracters 22 and 24, so that the input video signal Vi(t)
Complementary coefficients 1- and K for multiplying the delayed output video signal Vo (by -) are made possible by a single coefficient multiplier 23.
なお、この実施例の場合も、第1.第2の減算器16.
18及び振幅制限回路17による雑音低減と残像抑制の
原理は、前記実施例の場合とまったく同様である。In addition, in the case of this embodiment as well, the first. Second subtractor 16.
The principles of noise reduction and afterimage suppression by the amplitude limiting circuit 18 and the amplitude limiting circuit 17 are exactly the same as in the previous embodiment.
[発明の効果]
以上説明したように、この発明は、遅延用ディジタルメ
モリからなる遅延器を用いた雑音低減能力の高い巡回型
雑音低減器から得られる出力映像信号を、入力映像信号
から減算することにより、入力映像信号中の雑音成分と
動画成分を抽出し、振幅制限回路にて動画成分について
一定の振幅制限を施したのち、再び人力映像信号から減
算することで、雑音成分の除去と残像効果の抑制を図る
構成としであるため、従来の動き検出器のような複雑な
回路を用いることなく、2個の減算器と振幅制限回路を
1個用意することで、動き検出器と同等の効果を挙げる
ことができ、これにより装置全体の製造コストを低減し
、しかも高品位の雑音低減効果を挙げることができる等
の優れた効果を奏する。[Effects of the Invention] As explained above, the present invention subtracts an output video signal obtained from a cyclic noise reducer having a high noise reduction ability using a delay device made of a delay digital memory from an input video signal. By extracting the noise component and video component from the input video signal, applying a certain amplitude limit to the video component using the amplitude limiting circuit, and subtracting it from the human video signal again, the noise component can be removed and the afterimage can be removed. Since the structure is designed to suppress the effect, it can be equivalent to a motion detector by providing two subtractors and one amplitude limiting circuit, without using a complicated circuit like a conventional motion detector. As a result, the manufacturing cost of the entire device can be reduced, and a high-quality noise reduction effect can be achieved.
また、この発明は、振幅制限回路を、振幅制限レベルが
随意可変の構成としたから、入力映像信号に含まれる雑
音成分の程度に応じて振幅制限レベルを可変することで
、巡回型雑音低減により低減できる雑音成分とこれと同
レベルの動画成分だけを残すようにして、不要な動画成
分を取り除くことが可能であり、残像抑制を図ったため
に雑音低域の効果が薄れるといった不都合を、最大限押
さえ込むことができる等の効果を奏する。Furthermore, since the amplitude limiting circuit is configured to have an amplitude limiting level that is arbitrarily variable, the present invention can achieve cyclic noise reduction by varying the amplitude limiting level according to the degree of noise components included in the input video signal. It is possible to remove unnecessary video components by leaving only the video components at the same level as the noise components that can be reduced, and to minimize the inconvenience that the effect of the low noise range is weakened due to afterimage suppression. It has the effect of being able to be held down.
第1図は、この発明の巡回型雑音低減装置の一実施例を
示す回路構成図、第2図は、この発明の巡回型雑音低減
装置の他の実施例を示す回路構成図、第3図は、従来の
巡回型雑音低減装置の一例を示す回路構成図である。
11.21.、、巡回型雑音低減装置、15゜25、、
、巡回型雑音低減器、16.、、第1の減算器、17.
、、振幅制限回路、18.、、第2の減算器、20.、
、遅延器、Rv、、、可変抵抗。FIG. 1 is a circuit diagram showing one embodiment of the cyclic noise reduction device of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the cyclic noise reduction device of the invention, and FIG. 1 is a circuit configuration diagram showing an example of a conventional cyclic noise reduction device. 11.21. ,,cyclic noise reduction device, 15°25,,
, cyclic noise reducer, 16. ,,first subtractor,17.
, , amplitude limiting circuit, 18. ,, second subtractor, 20. ,
, delay device, Rv, , variable resistance.
Claims (2)
用ディジタルメモリからなる遅延器により、1フィール
ド期間にもっとも近い整数ライン期間又は1フレーム期
間だけ遅延した映像信号を、遅延前の映像信号に適宜の
比率でもって加算し、続いて前記遅延器による遅延に供
することで、映像信号中の信号成分と異なりフィールド
相関又はフレーム相関をもたない雑音成分を巡回的に低
減する巡回型雑音低減器と、この巡回型雑音低減器への
入力映像信号から出力映像信号を減算する第1の減算器
と、この第1の減算器の出力を振幅制限する振幅制限回
路と、この振幅制限回路の出力を前記入力映像信号から
減算する第2の減算器とを設けてなる巡回型雑音低減装
置。(1) A delay device consisting of a delay digital memory in which an AD converter and a DA converter are connected back and forth converts a video signal delayed by an integer line period closest to one field period or one frame period into the pre-delayed image. Cyclic noise that is added to a signal at an appropriate ratio and then delayed by the delay device to cyclically reduce noise components that have no field correlation or frame correlation unlike signal components in a video signal. a first subtracter that subtracts an output video signal from an input video signal to the cyclic noise reducer; an amplitude limiting circuit that limits the amplitude of the output of the first subtracter; and the amplitude limiting circuit. a second subtracter that subtracts the output of the input video signal from the input video signal.
の構成であることを特徴とする特許請求の範囲第1項記
載の巡回型雑音低減装置。(2) The cyclic noise reduction device according to claim 1, wherein the amplitude limiting circuit has a configuration in which the amplitude limiting level is arbitrarily variable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61225322A JPS6380687A (en) | 1986-09-24 | 1986-09-24 | Cyclic type noise reducing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61225322A JPS6380687A (en) | 1986-09-24 | 1986-09-24 | Cyclic type noise reducing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6380687A true JPS6380687A (en) | 1988-04-11 |
Family
ID=16827538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61225322A Pending JPS6380687A (en) | 1986-09-24 | 1986-09-24 | Cyclic type noise reducing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6380687A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323238A (en) * | 1987-07-07 | 1994-06-21 | Canon Kabushiki Kaisha | Image signal processing apparatus having improved storage control in accordance with an image signal level |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57212883A (en) * | 1981-06-25 | 1982-12-27 | Victor Co Of Japan Ltd | Noise reduction circuit |
| JPS6054579A (en) * | 1983-09-05 | 1985-03-29 | Victor Co Of Japan Ltd | Noise reducing device |
| JPS61150473A (en) * | 1984-12-24 | 1986-07-09 | Sony Corp | Noise eliminator |
-
1986
- 1986-09-24 JP JP61225322A patent/JPS6380687A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57212883A (en) * | 1981-06-25 | 1982-12-27 | Victor Co Of Japan Ltd | Noise reduction circuit |
| JPS6054579A (en) * | 1983-09-05 | 1985-03-29 | Victor Co Of Japan Ltd | Noise reducing device |
| JPS61150473A (en) * | 1984-12-24 | 1986-07-09 | Sony Corp | Noise eliminator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323238A (en) * | 1987-07-07 | 1994-06-21 | Canon Kabushiki Kaisha | Image signal processing apparatus having improved storage control in accordance with an image signal level |
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