JPS638492B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a control method for speeding up branch instructions in a pipeline-controlled data processing device.

(b) Background of the technology In pipeline-controlled data processing devices, it is important to minimize the "waiting" that occurs when no data or instructions exist in the cache memory, and to ensure that the instruction sequence meets the branch condition. When a change is made due to establishment or interruption, there is a problem of how to smoothly carry out the change processing.

The above-mentioned "waiting" problem can be solved to some extent by increasing the cache memory capacity, but when it comes to changing the instruction sequence, it is difficult to read the branch destination instruction in a branch instruction as early as possible. The key is to do it.

On the other hand, with the recent trend toward higher integration of logic circuits, it would be desirable to realize a hardware configuration that can reduce the number of input/output terminals of the logic block even if the number of logic elements increases somewhat when configuring a certain logic function. , the performance of the entire system is on the rise.

The present invention focuses on this point and attempts to speed up branch instructions in a pipeline-controlled data processing device.

(c) Prior Art and Problems FIG. 1 is a diagram schematically showing the pipeline operation in a conventional pipeline-controlled data processing device, in which I1 to I3 are instruction read pipes for fetching instructions. Showing each stage of the line,
P1 to P6 indicate each stage of the instruction execution pipeline for executing operand fetches and operations.

With reference to this diagram, first, general operations in a pipeline-controlled data processing device will be explained.

Initially, I1 of the pipeline of this data processing device
At this stage, the start address of the program to be executed from now on is set in the instruction address register (hereinafter referred to as IAR) 1A from the service processor (not shown). At this time, instruction fetch constant register (hereinafter referred to as IFKR) 1B
Since "0" is set in IAR1A, the contents of IAR1A are stored in adder (A)2 in stage I2.
Through A, the execution address register (hereinafter referred to as EAR)
The cache memory 4 is accessed by the EAR3, and the instruction is read into the instruction word register (hereinafter referred to as IWR) 5 at the end of the I3 stage.

Above, after the first instruction reading, the fixed value "8" is set by the instruction fetch control unit (IFC) 1.
Set to IFKR1B, IAR1A and adder (A) 2A
, the execution address is calculated, and EAR3
It operates as if it were set to . As a result,
Instructions are read to IWR5 in units of 8 bytes.

The IWR 5 described above is generally composed of a multi-stage shift register, and a pointer register (not shown) allows the boundary addresses of a plurality of instructions stored in the IWR 5 to be known.

A selector (SEL) 6 selects an instruction to be executed in the pipeline based on the address indicated by the pointer register.

When the instruction is selected by the selector (SEL) 6 in the P1 stage of the pipeline, the operation section of the instruction is operated at each P2 stage to P6.
Each operation register P corresponds to the stage.
2 OP to P6 OP (8) and used when executing instructions at each stage.

Each register specification part of the instruction is decoded,
Depending on the decoded address, general-purpose registers are accessed, and the respective base registers (BR) are
9, read out to index register (XR) 10.

The displacement designation part of the instruction is read into the displacement register (DR) 11.

Next, in the P2 stage, the base register (BR) 9 and the index register (XR)
10 and displacement register (DR)
11 is calculated in the adder (B) 12, and the operand address is calculated and stored in the target register (P3TAR) 13 of the P3 stage.
The cache memory 4 is accessed to perform an operand fetch.

The result of the operand fetch is read out to the operand word register (OWR) 15 at the end timing of the P4 stage, and is operated in the arithmetic circuit 16 at the next P5 stage, and the operation result is read out at the first timing of the P6 stage. is set in result register (RR) 17, and the same P6
It is stored in the general-purpose register 7 at the stage.

In the I1 stage described above, in addition to the instruction execution address calculation, the following operations are performed.

That is, when calculating an instruction execution address, each time a fixed value (for example, "8") is set in the instruction fetch constant register (IFKR) 1B, which is one input register of the adder (A) 2A, the counter is (CTR) Add the same fixed value as above to 1C.

Then, the instruction code that exits the pipeline is
The instruction operation unit register (P
6 OP) to the instruction fetch control unit (IFC) 1, and by determining the instruction type here, the length (number of bytes) of the instruction that has exited the pipeline is known, and the adder (C) 2B operates to subtract from the counter (CTR) 1C.

As a result, the counter (CTR) 1C has the following:
It contains the length of all instructions currently being processed in the pipeline, and means [IAR 1A] - [Counter (CTR) 1C] = the address of the instruction at the P6 stage.

If this operation is necessary, it is performed by subtracting the value of the counter (CTR) 1C from the IAR 1A using the adder (A) 2A.

As described above, one feature of the conventional system is that the instruction address register for reading instructions and the instruction address register indicating the address of the instruction being executed in the pipeline are shared.

The above is the operation of a general instruction, but the operation of a branch instruction related to the present invention will be explained next with reference to the time chart of FIG.

The instruction currently read to IWR5 (indicated by n)
If is a branch instruction, the operand address calculated by the adder (B) 12 indicates the branch destination address, and this address is stored and shifted in the target registers P3TAR to P6TAR of each stage of P3 to P6. At the same time, in the P2 stage (I1 stage for the branch destination instruction), it is set to EAR3 through the OR circuit 2C, the cache memory 4 is accessed, and the branch destination instruction (indicated by m, m+1...) is read out. It can be done.

In this P4 stage, an operation is performed on the instruction (indicated by n-1) immediately before the branch instruction (P5 stage for the n-1 instruction), and depending on the operation result, the branch When the condition is satisfied, the accessed branch destination instruction is read into the IWR 5, and each stage of P1 to P6 of the branch destination instruction is executed.

In the time chart of FIG. 3, the branch destination instruction (however, the instruction read at this time is
Byte instruction) operation in the pipeline (P
1 to P6 stages) are indicated by m and m+1.

In this conventional method, the following branch destination instruction m+2
When reading out the branch destination address stored in the target register P6TAR at the P6 stage of the branch instruction n, the branch destination address is read through the OR circuit 19.
IAR1A of the branch instruction m+2.
At the stage, adder (A) 2A adds the value of IFKR1B (“8”) to 8 of the address of branch instruction m.
The execution address of the byte destination is at the I2 stage.
EAR3 is set, cache memory 4 is accessed, and instruction m+2 is read.

After all, in the conventional method, P6 of branch instruction n
After the stage ends, stages I1 to I3 for reading the m+2 branch destination instruction will be executed. After this, P1 to P6 of the m+2 instruction
As it is clear from the time chart in FIG. 3, the stage is executed, so there will be a delay of three cycles from the instruction m+1.

In the conventional method, the branch instruction is executed, the branch condition is met, and there is no problem with the execution timing of the branch destination instruction that is read in advance, but the subsequent 8-byte branch destination instruction is read from the cache memory. The problem is that the read timing is delayed (specifically, as described above, the I1 stage starts after the execution of the branch instruction reaches the P6 stage).

As above, set the branch destination address to P of the branch instruction.
Up to 6th stage, target register P3TAR~
What needs to be maintained by P6TAR is P
This is because the contents of IAR1A cannot be changed at least until the branch instruction exits the pipeline because in stage 6, an error check is performed on the operation result, such as whether an interrupt occurred during the execution of the branch instruction. .

For example, if an error is detected in the P6 stage, the execution of the branch instruction will be invalidated, so the instruction must be retried, and it is essential to obtain the retry address from IAR1A. It is from.

To summarize the problems of the conventional method, in the conventional method, the instruction address register for reading instructions and the instruction address register indicating the address of the instruction being executed in the pipeline are shared; Since there is a possibility that an interrupt or error may occur during pipeline processing, the address of the branch instruction must be retained by some means even after the branch instruction has been decided until the branch instruction is completed. This causes a time delay in reading the instruction 8 bytes ahead of the branch destination.

Note that the route from the result register (RR) 17 to the OR circuit 19 is used, for example, when branching by a load PSW (program status word) instruction.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides a pipeline control data processing device that enables retry in the event of an error and provides a branching system that is necessary when executing a branch instruction and branching. The object of this invention is to provide a method for quickly reading an instruction 8 bytes ahead of a destination address.

(e) Structure of the Invention According to the present invention, the present invention provides an instruction read pipeline, a plurality of operation unit registers that hold the operation unit of the instruction being executed in each stage, and a branch target instruction when executing a branch instruction. It consists of an instruction execution pipeline equipped with multiple target registers that hold addresses of addresses at each stage, and when a branch destination address is calculated during execution of a branch instruction, the branch destination instruction is In a pipeline-controlled data processing device that reads an instruction in parallel with the execution of the branch instruction in an instruction read pipeline based on an address, a first instruction that holds an instruction address for reading an instruction by the instruction read pipeline; Generates the instruction length of the instruction being executed in the final stage from the contents of the address register, the second instruction address register that holds the address of the instruction being executed in the final stage of the instruction execution pipeline, and the final stage operation register. and an instruction length generation circuit to set the first instruction address register to either the contents of the second instruction address register or the contents of the target register of the corresponding stage when the branch condition is met during execution of a branch instruction. At the start of processing a series of programs, the address of the same first instruction is set in the first and second instruction address registers, and thereafter, the address of the same first instruction is set in the first instruction address register. , a constant is added every time one stage progresses, and the held contents are incremented to the address of the next instruction, and the second instruction address register stores the instruction length by the instruction length generation circuit at the time of completion of execution in the final stage. During instruction execution in the final stage, the address of the oldest instruction being executed in the pipeline is held, and if a branch condition is met during execution of a branch instruction, the contents of the target register of the relevant stage are added. is set in the first instruction address register via an OR circuit, and
If there is a change in the instruction sequence other than when the branch condition is met, the contents of the second instruction address register are set to the first instruction address register via the OR circuit, and the instructions of the new instruction sequence are read. This is achieved by a pipeline control method characterized by The address of the branch instruction for retry on error is held in the instruction address register during the final stage of execution of this instruction, so the instruction address register can be updated when the branch instruction is decided to branch. , there is an advantage that a delay in reading an instruction 8 bytes ahead of the branch destination can be eliminated.

(f) Embodiments of the Invention To summarize the gist of the present invention, the present invention independently provides an instruction address register for reading instructions and an instruction address register indicating the address of the instruction being executed in the pipeline. The address of the branch instruction is held in the instruction address register until the instruction exits the pipeline, and when the branching of the branch instruction is determined, the instruction address register can be updated and the branch destination This eliminates the delay in reading an instruction 8 bytes ahead of the 8 bytes.

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a time chart showing the operation of the embodiment of FIG. 2 when a branch instruction is executed.

In Figure 2, 1A, 1B, 2A, 2C, 3
1 to 19 are the same as those explained in FIG. 1, and 20 to 22 are logic blocks necessary to implement the present invention. Configure. That is, 20 is an instruction length generation circuit (ILC),
21 is an instruction address register (IAR), 22
is the adder D.

When the present invention is implemented, the instruction address registers (IAR) for reading the above-mentioned instructions, which are other features, are 1A, 1B, and 2 as explained in FIG.
It is composed of A.

As described above, when the present invention is implemented, the point is that the instruction address register and the instruction address register are configured independently.

The general pipeline operation when implementing the present invention is the same as the conventional one, so the explanation will be omitted, and we will focus on the effect of executing a branch instruction, with reference to the time chart in Figure 4. An example will be explained.

Even when the present invention is implemented, in the 11th stage of the pipeline of the present data processing device, the service processor (not shown)
two instruction address registers, [IAR()1
A, IAR()21] is set to the start address of the program to be executed from now on.

and instruction address register (IAR) 1
A has the same operation as the conventional method, but in the instruction address register (IAR) 21, each time the execution of one instruction is completed in the P6 stage of the pipeline, the instruction length of the instruction is determined by the instruction length generation circuit ( ILC) 20 and is added to the instruction address register (IAR), so until this addition operation is performed, the address of the oldest instruction executed in the pipeline is held. There will be.

Therefore, even when a branch instruction is executed, the address of the branch instruction is held in the instruction address register (IAR) 21 until the branch instruction leaves the pipeline.

Below, in the same way as the explanation in Figures 1 and 3,
Branch instruction is n, branch destination instruction is m, m+1, m+2
It will be explained as follows.

First, the instruction read to IWR5 (indicated by n)
If is a branch instruction, the operand address calculated by the adder (B) 12 indicates the branch destination address, and is accumulated and shifted in the target registers P3TAR to P6TAR of each stage of P3 to P6, and At the P2 stage (I1 stage for the branch destination instruction), the branch destination instruction (m, m+1...) is set to EAR3 through the OR circuit 2C, and the cache memory 4 is accessed.
) is read out.

Then, in the P4 stage, the operation of the instruction (n-1) immediately before the branch instruction is performed (that is, the P5 stage), and based on the result of the operation,
When the branch condition is met, the accessed branch instruction is read out to IWR5 at the end of the I3 stage, and then each stage of P1 to P6 of the branch destination instruction is executed.

In the time chart of FIG. 4, the branch destination instruction (however, the instruction read at this time is
Byte instruction) operation in the pipeline (P
1 to P6 stages) are indicated by m and m+1.

As is clear from this figure, the operation up to this point is the same as the conventional system.

When reading the subsequent branch destination instruction m+2, in the present invention, the branch destination address stored in the target register P4TAR is read through the OR circuit 23 at the P4 stage of the branch instruction n.
IAR() is set to 1A, branch destination instruction m+2
In the I1 stage of the adder (A) 2A, IFKR1
The value of B ("8") is added, and the execution address 8 bytes ahead of the address of the branch destination instruction m is set to EAR3 at the I2 stage.

Therefore, when the present invention is implemented, the branch instruction P
At the end of the 4th stage, the execution of stages I1 to I3 for reading the branch destination instruction m+2 is started, so the read operation of branch destination instructions m and m+1 (i.e. stage I1 to I3) and the branch destination instruction m+2 are started. There is no delay between the reading operation (stages I1 to I3) of the instruction m+2 which is 8 bytes ahead of the previous instruction m. Then, after this, P1 to P of the m+2 instruction
Since six stages are executed, the delay from the m+1 instruction is reduced to one cycle, as is clear from the time chart of FIG.

As described above, when the present invention is implemented, in order to start executing the I1 to I3 stages for reading the branch destination instruction m+2 at the P4 stage of the branch instruction n, the address of the m+2 instruction is set in IAR()1A. set and destroy the address of branch instruction n, but
As mentioned above, the address of the branch instruction is held in the instruction address register (IAR) 21 until the branch instruction exits the P6 stage.
As explained in the conventional method, even if an error is detected at the P6 stage and it becomes necessary to retry the branch instruction, the contents of the instruction address register (IAR) 21 are transferred to the adder (D) 22 and the OR circuit. No problem occurs because the instruction can be reread by resetting the instruction address register (IAR) 1A through 19 and 23. This is the key point of the present invention.

(g) Effects of the Invention As explained above in detail, the pipeline control method of the present invention has an instruction address register for reading instructions and an instruction register indicating the address of the instruction being executed in the final stage of the pipeline. The address of the branch instruction is kept independent from the address register, and the address of the branch instruction is held in the instruction address register until the instruction leaves the pipeline, and the branch of the branch instruction is determined. When the branch instruction is executed and the branch condition is met, the instruction address register can be updated and the delay in reading the instruction 8 bytes ahead of the branch destination is eliminated. However, it has the effect of reducing the cycle loss that occurs in the pipeline and speeding up branch instructions.

[Brief explanation of the drawing]

Fig. 1 is a diagram schematically showing the pipeline operation of the conventional method, Fig. 2 is a diagram schematically showing the pipeline operation when the present invention is implemented, and Fig. 3 is a diagram schematically showing the pipeline operation of the conventional method. , a time chart showing the operation when a branch instruction is executed.
FIG. 3 is a time chart showing the operation when a branch instruction is executed. In the drawing, 1 is an instruction fetch control unit (IFC), 1A is an instruction address register (IAR),
Instruction address register (IAR), 1B is instruction fetch constant register (IFKR), 1C
is a counter (CTR), 2A, 2B, 12, 22 are adders (A, C, B, D), 3 is an execution address register (EAR), 4 is a cache memory, 5 is an instruction word register (IWR), 6 is a selector, 7 is a general-purpose register, and 8 is an operation register (P2OP to P6
OP), 18 is the target register (P3TAR~
P6TAR), 20 is the instruction length generation circuit (ILC), 2
1 indicates an instruction address register (IAR).

Claims (1)

[Claims] 1. An instruction read pipeline, a plurality of operation unit registers that hold the operation unit of the instruction being executed at each stage, and a plurality of operation unit registers that hold the address of the branch destination instruction at each stage when a branch instruction is executed. When a branch destination address is calculated during execution of a branch instruction, the branch destination instruction is transferred to the instruction read pipeline using the calculated address before the branch condition is satisfied. In a pipeline-controlled data processing device that performs reading in parallel with the execution of an instruction, there is a first instruction address register that holds an instruction address for reading an instruction by an instruction read pipeline, and a first instruction address register that holds an instruction address for reading an instruction by an instruction read pipeline; a second instruction address register that holds the address of the instruction being executed in the stage; an instruction length generation circuit that generates the instruction length of the instruction being executed in the final stage from the contents of the operation unit register in the final stage; An OR circuit is provided for the instruction address register to select whether to set the contents of the second instruction address register or the contents of the target register of the corresponding stage when the branch condition is met during execution of a branch instruction. At the start of program processing, the address of the same first instruction is set in the first and second instruction address registers, and from then on, a constant is added to the first instruction address register every time one stage progresses. The stored content is incremented to the address of the next instruction, and the instruction length generated by the instruction length generation circuit is added to the second instruction address register at the time of completion of execution in the final stage. During execution, the address of the oldest instruction being executed in the pipeline is held, and when a branch condition is met during execution of a branch instruction, the contents of the target register of the corresponding stage are transferred to the first instruction address register via an OR circuit. In addition, if there is a change in the instruction sequence other than when the branch condition is met, the contents of the second instruction address register are set to the first instruction address register via the OR circuit, and a new instruction is issued. A pipeline control method characterized by reading instructions in an instruction sequence.