JPS6387933U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram of an example of a conventional reception clock signal regeneration circuit, and Figure 3 is the fixed frequency divider 6 in Figure 1.
FIG. 3 is a diagram showing a time relationship when the frequency division ratio of is set to 1/2. 1... Input terminal, 2... Phase comparison circuit, 3... Frequency division ratio control circuit, 4... Master clock generator, 5... Variable frequency divider, 6... Fixed frequency divider, 7... Frequency switching circuit, 8... Fixed Frequency divider, 9...Output terminal, 10...External terminal, 11...Selector switch.

Claims (1)

[Claims for Utility Model Registration] A master clock generator, a variable frequency divider, a fixed frequency divider, a phase change signal extracted from received data, and an output frequency of the master clock generator that is controlled by the variable clock generator. Compare the phases of the received and recovered clock signals obtained by dividing the frequency with the frequency divider and fixed frequency divider,
a phase comparator circuit that detects a phase difference and outputs phase information, and after counting the phase information a certain number of times, increases or decreases the frequency division ratio of the variable frequency divider according to the phase information; In a reception clock signal regeneration circuit using a digital phase lock loop, which includes a frequency division ratio control circuit that counts the output frequency of a frequency divider by a fixed number and then resets it to the original frequency division ratio, the variable frequency divider and a fixed frequency division ratio control circuit are configured. A plurality of frequency dividers with different division ratios for dividing the output frequency of the variable frequency divider and a frequency switching circuit are provided between the variable frequency divider and the frequency division ratio. The frequency switching circuit is externally controlled to output frequencies of a plurality of different frequency dividers, and an external terminal is provided for connecting a changeover switch for obtaining a plurality of different reception and reproduction clock signals. A receiving clock signal regeneration circuit with a clock signal switching circuit for digital communication equipment.