JPS6392425U - - Google Patents

Info

Publication number
JPS6392425U
JPS6392425U JP18775586U JP18775586U JPS6392425U JP S6392425 U JPS6392425 U JP S6392425U JP 18775586 U JP18775586 U JP 18775586U JP 18775586 U JP18775586 U JP 18775586U JP S6392425 U JPS6392425 U JP S6392425U
Authority
JP
Japan
Prior art keywords
output
converter
phase
gain control
control amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18775586U
Other languages
Japanese (ja)
Other versions
JPH0614511Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18775586U priority Critical patent/JPH0614511Y2/en
Publication of JPS6392425U publication Critical patent/JPS6392425U/ja
Application granted granted Critical
Publication of JPH0614511Y2 publication Critical patent/JPH0614511Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係る位相同期受信
機を示すブロツク図、第2図は従来の位相同期受
信機を示すブロツク図である。 1:混合器、2:利得制御増幅器、3:位相検
波器、4:電圧制御発振器、5:信号切替器、7
:同期検波器、9:基準信号発生器、10:A/
D変換器、11:メモリ、12:マイクロプロセ
ツサ、13:D/A変換器。
FIG. 1 is a block diagram showing a phase-locked receiver according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional phase-locked receiver. 1: Mixer, 2: Gain control amplifier, 3: Phase detector, 4: Voltage control oscillator, 5: Signal switch, 7
: Synchronous detector, 9: Reference signal generator, 10: A/
D converter, 11: memory, 12: microprocessor, 13: D/A converter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 受信信号を周波数変換するための混合器と、上
記混合器の出力を増幅する利得制御増幅器と、こ
の利得制御増幅器の出力信号の位相を検出する位
相検波器と、この位相検波器の出力により位相同
期ループを形成して上記混合器の出力周波数を制
御する電圧制御発振器と、上記利得制御増幅器の
出力振幅を検出しAGCループを形成して上記利
得制御増幅器の出力振幅を利得する同期検波器と
、上記位相検波器および上記同期検波器の各出力
をA/D変換するA/D変換器と、このA/D変
換器からの出力信号を記憶するメモリと、上記A
/D変換器でA/D変換されたデータにもとづき
上記位相同期ループを制御して、複数の受信信号
のうちからその中心の周波数をもつ信号を受信さ
せるプロセツサとを具備したことを特徴とする位
相同期受信機。
a mixer for frequency converting the received signal; a gain control amplifier for amplifying the output of the mixer; a phase detector for detecting the phase of the output signal of the gain control amplifier; a voltage controlled oscillator that forms a synchronous loop to control the output frequency of the mixer; and a synchronous detector that detects the output amplitude of the gain control amplifier and forms an AGC loop to gain the output amplitude of the gain control amplifier. , an A/D converter that A/D converts each output of the phase detector and the synchronous detector, a memory that stores the output signal from the A/D converter, and the A/D converter that stores the output signal from the A/D converter;
and a processor that controls the phase-locked loop based on data A/D converted by the A/D converter to receive a signal having a center frequency from among a plurality of received signals. Phase-locked receiver.
JP18775586U 1986-12-04 1986-12-04 Phase synchronization receiver Expired - Lifetime JPH0614511Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18775586U JPH0614511Y2 (en) 1986-12-04 1986-12-04 Phase synchronization receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18775586U JPH0614511Y2 (en) 1986-12-04 1986-12-04 Phase synchronization receiver

Publications (2)

Publication Number Publication Date
JPS6392425U true JPS6392425U (en) 1988-06-15
JPH0614511Y2 JPH0614511Y2 (en) 1994-04-13

Family

ID=31138511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18775586U Expired - Lifetime JPH0614511Y2 (en) 1986-12-04 1986-12-04 Phase synchronization receiver

Country Status (1)

Country Link
JP (1) JPH0614511Y2 (en)

Also Published As

Publication number Publication date
JPH0614511Y2 (en) 1994-04-13

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