JPS6410108B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a nonvolatile semiconductor memory device.

Semiconductor memory devices using conventional insulated gate field effect transistors (hereinafter referred to as IGFETs) have the disadvantage that stored information is lost when the power is turned off. Several nonvolatile semiconductor memory devices have been developed to compensate for this drawback. These memory elements associate the magnitude of threshold voltage with binary information, and store this information in a non-volatile manner even when the power is cut off.

By the way, the above nonvolatile semiconductor memory element is
In terms of write/erase times and speed, there are practical problems that ordinary IGFETs do not have. Figure 1 shows
It has been developed as a solution to these problems, and it combines a bistable circuit consisting of an IGFET with a nonvolatile semiconductor memory element. Normally, information is stored in the bistable circuit, and the information in the bistable circuit is transferred when the power is cut off. It is written in a nonvolatile memory element and stored as nonvolatile information, and Q ₁ , Q ₂ ,
Q ₃ and Q ₄ are enhancement type IGFETs, Q ₅ and Q ₆ are depletion type IGFETs, and MT ₁ and MT connected in parallel with Q ₃ and Q ₄ , respectively.
MT ₂ is an MNOS memory transistor, Q ₁ , Q ₂ ,
_Q5 and _Q6 are ordinary flip-flops that constitute static memory cells. That is, when the power is applied, IGFETs _{Q 3} and Q ₄ are in a conductive state and operate as a flip-flop, and when the power is cut off, the information of the flip-flop is written to the MNOS memory transistors MT ₁ and MT ₂ , and the information content before the power is cut off is stored. The purpose is to store it in a non-volatile manner.

Figure 2 shows the characteristics of a well-known P-channel MNOS memory transistor, showing the hysteresis characteristics of the threshold voltage V _th with respect to the gate applied voltage V _G.
1msec), V _th moves in the positive direction to +2V, and when a negative pulse (e.g. -25V,
1msec), V _th moves in the negative direction to -6V. V _th set in this way is held non-volatile unless a voltage larger than the substrate or channel potential is applied to the gate.

The memory cell shown in Fig. 1 uses the hysteresis characteristics of the MNOS memory transistors MT ₁ and MT ₂ shown in Fig. 2 to respond when the power is cut off.
The potentials of the drains N ₁ and N ₂ of IGFETQ ₁ and Q ₂ cause the MNOS memory transistors MT ₁ and
The operation is such that flip-flop information is written to MT ₂ as the difference in threshold voltage, this is stored in a non-volatile manner, and when power is applied, the information of MT ₁ and MT ₂ is reproduced in the flip-flop.

By the way, the memory cell in Figure 1 is a normal
Compared to a flip-flop using only IGFETs, it has the disadvantage of having four more elements (IGFETQ ₃ , Q ₄ and MNOS transistors MT ₁ , MT ₂ ), so when a static RAM is configured, a transfer gate (not shown) is required. If you include them, there will be 10 elements, which will be very disadvantageous as the capacity increases.

The present invention focuses on the above points, and provides a nonvolatile semiconductor memory device that reduces the number of elements per memory cell and is advantageous for increasing capacity.

According to the present invention, there is provided a bistable circuit including a pair of insulated gate field effect transistors, in which the gate of one transistor and the drain of the other transistor are connected to each other, and two of the bistable circuits are connected to each other. Two nonvolatile insulated gate field effect memory transistors are inserted in series between the nodes with one insulated gate field effect transistor interposed between the two nonvolatile insulated gate field effect memory transistors. A common control signal line is connected to the gate, and another control signal line having an opposite phase to the control signal line is connected to the gate of the one insulated gate field effect transistor, and a predetermined signal line is connected to both control signal lines. A nonvolatile semiconductor memory device comprising a memory cell having means for nonvolatilely storing electrical information of the bistable circuit in the two nonvolatile insulated gate field effect transistors by applying a voltage of is obtained.

Next, embodiments of the present invention will be described.

FIG. 3 is a circuit connection diagram showing the configuration of a memory cell according to an embodiment of the present invention.
IGFETQ ₁₁ , Q ₁₂ and depletion type
IGFETQ ₁₃ and Q ₁₄ constitute a bistable circuit of normal static memory cells. An MNOS transistor MT ₁₁ is connected between the connection point N ₁₁ between the drain of IGFET Q ₁₁ and the source of Q ₁₃ and the connection point N ₁₂ between the drain of Q ₁₂ and the source of Q ₁₄ , which constitute this bistable circuit.
Connect MT ₁₂ and enhancement type IGFETQ ₁₅ in series. In this case, _Q15 is connected between _MT11 and _MT12 . The gates of MT ₁₁ and MT ₁₂ are commonly connected to the control signal line MG. The gate of _Q15 is connected to a control signal that is in opposite phase to MG.

When power is normally applied, this memory cell can continue to operate statically as a bistable circuit consisting of a normal IGFET.
By applying a signal voltage to MG, the information of the bistable circuit can be stored in MT ₁₁ and MT ₁₂ . When the information stored in MT ₁₁ and MT ₁₂ is needed, it can be used
After transferring to a bistable circuit consisting of an IGFET, normal static operation can be continued.

In FIG. 3, a memory operation using the MNOS memory transistor shown in FIG. 2 will be described in detail below. For convenience of explanation, it is assumed that the IGFETs _{Q 11} to Q ₁₅ and the MNOS memory transistors MT ₁₁ and MT ₁₂ are all P channels.
The threshold voltage of IGFETQ ₁₁ , Q ₁₂ , Q ₁₅ is -1.0V, the reference potential V _SS = 0V, the power supply voltage V _DD = -17V,
The threshold voltages V _TM1 and V _TM2 of the MNOS memory transistors MT ₁₁ and MT ₁₂ are assumed to be in the erased state V _TH0 =+2V and in the written state V _TH1 =-6V. And V _TM1 = V _TH0 =
+2V, V _TM2 = V _TH1 = -6V status is information “1”,
The opposite state is defined as information "0". On the other hand, the information of the bistable circuit is defined by the potentials V ₁ and V ₂ of N ₁₁ and N ₁₂ , and is "1" when V ₁ -15V, V ₂ = 0V, and conversely, when V ₁ = 0V, V ₂ Set to “0” at −15V. First, at an appropriate time while the power is applied,
Control signal line connected to the gates of MT ₁₁ and MT ₁₂
Negative pulse voltage on MG (e.g. -25V, 1msec)
, and also the control signal line connected to the gate of Q ₁₅
By applying a positive pulse voltage (e.g. 0V, 1msec) to MG, the information of the bistable circuit is
Written to MT ₁₁ and MT ₁₂ . That is, if the information of the bistable circuit is "1", V ₂ =0V, so V _TM2 =-6V. On the other hand, at V ₁ −15V, V ₁
Since the voltage difference between and MG is effectively about -10V, writing to _MT1 is prohibited and V _TM1 is kept at +2V. In this way, the information of the bistable circuit is
It is written to MT ₁ and MT ₂ as a difference in threshold voltage and is stored non-volatilely.

Similarly, if the information of the bistable circuit is "0", MT ₁₁ and MT ₁₂ each have a threshold voltage V _TM1 =
+2V, V _TM2 = -6V is written, and this is stored non-volatilely.

To read the nonvolatile information of the MNOS memory transistors MT ₁₁ and MT ₁₂ and return them to a bistable circuit, connect the control signal line MG with 0V to +5V and the control signal line MG with 0V to +5V.
Apply a read signal with an amplitude of 0V to -5V to MG. Now, if MT ₁₁ and MT ₁₂ store information "1", V _TM1 = +2V, V _TM2 = -6V, so when the above read signal is applied to MG and MT ₁₁ , the channel is is formed,
There is no channel formation in MT ₁₂ . the result,
When the V _DD power supply is restored, |V ₁ |> |V ₂ |,
_Q12 becomes conductive first, and due to negative feedback
_Q11 is in the off state. In other words, information "1" is returned to the bistable circuit.

Similarly, if MT ₁₁ and MT ₁₂ store information "0", information "0" will be read into the bistable circuit.

With the memory cell configuration as described above, the number of elements is clearly reduced compared to the conventional configuration shown in FIG. Such a reduction in the number of elements also leads to a reduction in the number of signal lines inside the memory cell, which reduces the cell size of the integrated circuit and facilitates the realization of a large-capacity nonvolatile semiconductor memory device.

It should be noted that the present invention is not limited to the above-described embodiments, and for example, a configuration in which Q ₁₃ and Q ₁₄ of the bistable circuit are of the enhancement type is also possible. Further, it is needless to explain that in addition to the MNOS structure, an MIOS structure, a tunnel injection type structure having a floating gate, etc. can be used.

In addition, it goes without saying that the device used in the present invention may be an n-channel device.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram of a conventional nonvolatile semiconductor memory cell, FIG. 2 is a diagram showing hysteresis characteristics of a P-channel MNOS memory transistor, and FIG. 3 is a circuit connection diagram of a memory cell showing an embodiment of the present invention. It is. Q ₁₁ , Q ₁₂ , Q ₁₅ ... Enhancement type
IGFET, Q ₁₃ , Q ₁₄ ... Debretion type IGFET,
MT ₁₁ , MT ₁₂ ... Variable threshold MNOS memory transistor, V _DD ... Power supply voltage, V _SS ... Reference potential,
MG...Control signal line...Control signal line with opposite phase to MG.

Claims (1)

[Claims] 1. A bistable circuit formed by interconnecting the gate of one transistor and the output terminal of the other transistor of a pair of insulated gate field effect transistors, and a first nonvolatile circuit between each output terminal of the bistable circuit. a series circuit in which a nonvolatile insulated gate field effect transistor, an insulated gate field effect transistor, and a second nonvolatile insulated gate field effect transistor are connected in series in this order; A write voltage for writing information stored in the bistable circuit and a read voltage for reading the written information into the bistable circuit are applied to each gate of the nonvolatile insulated gate field effect transistor, A nonvolatile semiconductor memory device characterized in that a potential opposite in phase to the write voltage and the read voltage is applied to the gate of the insulated gate field effect transistor located between these.