JPS6410325A - Binary multiplication device - Google Patents

Binary multiplication device

Info

Publication number
JPS6410325A
JPS6410325A JP62167226A JP16722687A JPS6410325A JP S6410325 A JPS6410325 A JP S6410325A JP 62167226 A JP62167226 A JP 62167226A JP 16722687 A JP16722687 A JP 16722687A JP S6410325 A JPS6410325 A JP S6410325A
Authority
JP
Japan
Prior art keywords
data
circuit
adder
multiplicand
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62167226A
Other languages
Japanese (ja)
Inventor
Akihito Mochizuki
Toshiaki Watanabe
Mitsuo Togashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP62167226A priority Critical patent/JPS6410325A/en
Publication of JPS6410325A publication Critical patent/JPS6410325A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase the arithmetic speed and to simplify the circuit constitution for a binary multiplication device by using a combination circuit which produces a partial product from the multiplicand data and the decoded multiplier data. CONSTITUTION:A decoding circuit part 9 decodes the input 3-bit multiplier data B3-B1 and outputs the decoding signals e5-e1 corresponding to the value of the multiplier data. A selector circuit part 11 of a combination circuit 6 supplies two multiplication data to A channels 6A-1A and B channels 6B-1B of an adder 8 of an addition circuit 7 based on the input multiplicand data A3-A1 and the output signal e5-e1 received from the circuit 9. The adder 8 adds two input multiplication data together and outputs partial products X6-X1. When each bit of the 3-bit multiplier data is equal to 1, the value obtained by multiplying the multiplicand data by 8 and the value obtained by subtracting the complement of the multiplicand data are supplied to the adder 8 via an inverting circuit part 10.
JP62167226A 1987-07-03 1987-07-03 Binary multiplication device Pending JPS6410325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62167226A JPS6410325A (en) 1987-07-03 1987-07-03 Binary multiplication device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62167226A JPS6410325A (en) 1987-07-03 1987-07-03 Binary multiplication device

Publications (1)

Publication Number Publication Date
JPS6410325A true JPS6410325A (en) 1989-01-13

Family

ID=15845785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62167226A Pending JPS6410325A (en) 1987-07-03 1987-07-03 Binary multiplication device

Country Status (1)

Country Link
JP (1) JPS6410325A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332212A (en) * 1989-06-29 1991-02-12 Mitsubishi Electric Corp Signal processing circuit for multiplication
US5781462A (en) * 1994-11-29 1998-07-14 Mitsubishi Denki Kabushiki Kaisha Multiplier circuitry with improved storage and transfer of booth control coefficients

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371729A (en) * 1986-09-12 1988-04-01 Matsushita Electric Ind Co Ltd arithmetic processing unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371729A (en) * 1986-09-12 1988-04-01 Matsushita Electric Ind Co Ltd arithmetic processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332212A (en) * 1989-06-29 1991-02-12 Mitsubishi Electric Corp Signal processing circuit for multiplication
US5781462A (en) * 1994-11-29 1998-07-14 Mitsubishi Denki Kabushiki Kaisha Multiplier circuitry with improved storage and transfer of booth control coefficients

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