JPS6410331A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6410331A
JPS6410331A JP62165337A JP16533787A JPS6410331A JP S6410331 A JPS6410331 A JP S6410331A JP 62165337 A JP62165337 A JP 62165337A JP 16533787 A JP16533787 A JP 16533787A JP S6410331 A JPS6410331 A JP S6410331A
Authority
JP
Japan
Prior art keywords
address
csar
speed
field
csdr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62165337A
Other languages
Japanese (ja)
Inventor
Hiromichi Kaino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62165337A priority Critical patent/JPS6410331A/en
Publication of JPS6410331A publication Critical patent/JPS6410331A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE:To improve the processing performance for reading control by securing selection between a high-speed control storage CS and a low-speed CS in response to the executing characteristics of a microprogram. CONSTITUTION:When an address 1 is inputted to a CSAR 3, a high-speed CS1 receives an access in a single machine cycle MC and the data 1-H on the CS1 of the address 1 is set at a CSDR 4 since the address 1 designates the CS1. At the same time, the 1-H, i.e., an address 2 is set at the CSAR 3 in the next cycle CS address field 41. As a result, the reading requests are applied simultaneously to both the CS1 and a low-speed CS2. The CS1 passes through a selector 8 after 1MC and is set at the CSDR 4. Then the field 41 is set at the CSAR 3 since the address 2 is designated to the field 41. However the CSAR 3 is not updated owing to the same data. Thus the read data is assured at the side of the CS2.
JP62165337A 1987-07-03 1987-07-03 Information processor Pending JPS6410331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165337A JPS6410331A (en) 1987-07-03 1987-07-03 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165337A JPS6410331A (en) 1987-07-03 1987-07-03 Information processor

Publications (1)

Publication Number Publication Date
JPS6410331A true JPS6410331A (en) 1989-01-13

Family

ID=15810418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165337A Pending JPS6410331A (en) 1987-07-03 1987-07-03 Information processor

Country Status (1)

Country Link
JP (1) JPS6410331A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03260832A (en) * 1990-03-12 1991-11-20 Fujitsu Ltd Microprogram controller
US7628342B2 (en) 2004-05-11 2009-12-08 Daiwa Can Company Liquefied gas dispensing nozzle and liquefied gas dispensing apparatus
JP2024069323A (en) * 2016-06-27 2024-05-21 アップル インコーポレイテッド Memory system combining high density, low bandwidth memory and low density, high bandwidth memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03260832A (en) * 1990-03-12 1991-11-20 Fujitsu Ltd Microprogram controller
US7628342B2 (en) 2004-05-11 2009-12-08 Daiwa Can Company Liquefied gas dispensing nozzle and liquefied gas dispensing apparatus
JP2024069323A (en) * 2016-06-27 2024-05-21 アップル インコーポレイテッド Memory system combining high density, low bandwidth memory and low density, high bandwidth memory

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