JPS6410405A - Reproduction equalizing circuit - Google Patents

Abstract

PURPOSE:To obtain an optimum characteristic in response too the tap running speed by using a semiconductor delay circuit as a delay circuit and varying a clock signal frequency so as to obtain a desired delay time. CONSTITUTION:A digital signal f(t+tau) regenerated from a magnetic tape comes to an input terminal 25 and fed sequentially to CCDs 27, 28 connected in cascade in two-stage. On the other hand, a clock signal generating circuit 29 generates a clock signal having a sampling frequency so as to obtain an optimum delay time by using a control signal from an input terminal 26. The level of the signal f(t+tau) from the terminal 25 is adjusted by a variable resistor 30 and the signal is fed to an adder circuit 32, where the signal is extracted from the CCD 28 and added to a digital signal whose level is adjusted by a variable resistor 31. A differential amplifier 33 applies differential amplification between a delayed digital signal from the CCD 27 and a synthesized digital signal from the circuit 32 and gives the result from a terminal 34. Thus, the waveform of the regenerated digital signal is divided minutely and the waveform interruption is reduced.