JPS6411449A - Symbol carrier timing regeneration system - Google Patents

Abstract

PURPOSE:To widen a lead-in range for a carrier frequency offset and to simplify a circuit by providing a means which extracts a clock component by a decision directed system and a means which detects a carrier phase error. CONSTITUTION:The extracting means consisting of rectifying circuits 8 and 9 and a subtracting circuit 12 which rectify an in-phase and an orthogonal output and find their difference to obtain a frequency component a half as high as a symbol clock, and a decision directed type phase-locked loop (phase detectors 13 and 14, loop filter 19, VCO 20, orthogonal phase branching filter 15, LPF 17, comparator 18, and multiplier 16) generates the clock component through the nonlinear operation of an orthogonal demodulation output and extracts this component by the decision directed system. The detecting means consisting of a data detecting circuit 4, a multiplier 5, a sample holding circuit 6, and a switch 7 samples one of a couple of orthogonal demodulated data alternately at intervals of one clock at clock timing obtained by the loop, multiplies the value by the demodulated data, and detects the carrier phase error.