JPS6412714A - Register with initialization circuit - Google Patents

Register with initialization circuit

Info

Publication number
JPS6412714A
JPS6412714A JP62169213A JP16921387A JPS6412714A JP S6412714 A JPS6412714 A JP S6412714A JP 62169213 A JP62169213 A JP 62169213A JP 16921387 A JP16921387 A JP 16921387A JP S6412714 A JPS6412714 A JP S6412714A
Authority
JP
Japan
Prior art keywords
clocked
time
register
phi1
phi1n
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62169213A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP62169213A priority Critical patent/JPS6412714A/en
Publication of JPS6412714A publication Critical patent/JPS6412714A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To diminish the scale of a circuit and to shorten an initializing time, by normalizing the levels of clocked logic and clocked feedback logic at the time of initialization. CONSTITUTION:At the time of starting up a register, an initial signal INI is set at a high level, and the input of a NAND gate CNA1 is set at a low level compulsorily. Simultaneously, clocks phi1 and phi1N are set at the low levels compulsorily by supplying the initial signal INI to NOR gates NR1 and NR2, then, the NAND gate CNA1 ON/OFF-controlled by the clock phi1, clocked inverters CK12-CK14 ON/OFF-controlled by the clocks phi1 and phi1N, and clocked inverters CI1-CI4 for feedback are intialized. In such a way, latches at all stages can be initialized to the low levels simultaneously.
JP62169213A 1987-07-07 1987-07-07 Register with initialization circuit Pending JPS6412714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62169213A JPS6412714A (en) 1987-07-07 1987-07-07 Register with initialization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62169213A JPS6412714A (en) 1987-07-07 1987-07-07 Register with initialization circuit

Publications (1)

Publication Number Publication Date
JPS6412714A true JPS6412714A (en) 1989-01-17

Family

ID=15882303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62169213A Pending JPS6412714A (en) 1987-07-07 1987-07-07 Register with initialization circuit

Country Status (1)

Country Link
JP (1) JPS6412714A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365440A (en) * 1990-11-30 1994-11-15 Honda Giken Kogyo Kabushiki Kaisha Four wheel steering system
US9885618B2 (en) * 2013-05-03 2018-02-06 3M Innovative Properties Company System for monitoring temperature of electrical conductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365440A (en) * 1990-11-30 1994-11-15 Honda Giken Kogyo Kabushiki Kaisha Four wheel steering system
US9885618B2 (en) * 2013-05-03 2018-02-06 3M Innovative Properties Company System for monitoring temperature of electrical conductor

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