JPS6413143U - - Google Patents
Info
- Publication number
- JPS6413143U JPS6413143U JP10542887U JP10542887U JPS6413143U JP S6413143 U JPS6413143 U JP S6413143U JP 10542887 U JP10542887 U JP 10542887U JP 10542887 U JP10542887 U JP 10542887U JP S6413143 U JPS6413143 U JP S6413143U
- Authority
- JP
- Japan
- Prior art keywords
- notch
- chip
- hole
- circuit board
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の一実施例の平面図、第２図は
第１図のものの−線に沿う断面図である。
１……放熱板、２……切欠き、３……基板、４
……ＩＣチツプ、５……ワイヤ。
FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line -- of FIG. 1. 1... Heat sink, 2... Notch, 3... Board, 4
...IC chip, 5...wire.
Claims (1)
基板の最下面を良熱伝導材からなる放熱板の上面
に接合し、該プリント基板の一部に切欠きまたは
孔を設け、該切欠きまたは孔にＩＣチツプをその
下面が前記放熱板に接するようにして挿入し、該
ＩＣチツプのボンデイングパツドと前記各基板と
の間をボンデイングワイヤにより接続したことを
特徴とする集積回路素子の保持構造。 The lowermost surface of a printed circuit board made of multiple laminated glass epoxy materials is bonded to the upper surface of a heat sink made of a good heat conductive material, a notch or hole is provided in a part of the printed circuit board, and an IC is inserted into the notch or hole. 1. A holding structure for an integrated circuit element, characterized in that a chip is inserted so that its lower surface is in contact with the heat sink, and bonding pads of the IC chip and each of the substrates are connected by bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10542887U JPS6413143U (en) | 1987-07-09 | 1987-07-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10542887U JPS6413143U (en) | 1987-07-09 | 1987-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6413143U true JPS6413143U (en) | 1989-01-24 |
Family
ID=31338032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10542887U Pending JPS6413143U (en) | 1987-07-09 | 1987-07-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6413143U (en) |
-
1987
- 1987-07-09 JP JP10542887U patent/JPS6413143U/ja active Pending